Abstract: A flat lightweight member includes fiber reinforced plastics and having excellent mechanical properties of an end portion and excellent adhesiveness between a core layer and a skin layer as well as good appearance quality and excellent producibility, the flat lightweight member includes a skin layer including a braiding material and a matrix resin, a separation layer having a bag shape and being present inside the braiding material, and a mixture of a matrix resin and a thermally expandable material, the mixture being present inside the separation layer.

Abstract: The installation structure of a sensor includes a sensor body, a holder provided with a locking part and configured to install the sensor body by locking the sensor body with the locking part, the locking part configured to deform when installing the sensor body to the holder and configured to restore when installation of the sensor body to the holder is completed, and a holder-installation body provided with an installable portion where the holder is to be installed and configured to prevent a deformation of the locking part of the holder.

Abstract: An artificial shuttlecock feather for implanting in a circular ring shape into a shuttlecock base, including: a vane section and a rachis section having one end in an axial direction of the rachis section fixed to the base and supporting the vane section provided to another end side of the rachis section, a hole being formed in the vane section so as to penetrate the vane section, and a porosity of a first region of the vane section being lower than a porosity of a second region of the vane section, the first region spanning from an edge on the one end side in the axial direction to a predetermined position further toward the one end side than a center of vane section in the axial direction, the second region spanning from the predetermined position to an edge on the other end side in the axial direction.

Abstract: An artificial shuttlecock feather for implanting in a circular ring shape into a shuttlecock base, including: a vane section and a rachis section having one end in an axial direction of the rachis section fixed to the base and supporting the vane section provided to another end side of the rachis section, a hole being formed in the vane section so as to penetrate the vane section, and a porosity of a first region of the vane section being lower than a porosity of a second region of the vane section, the first region spanning from an edge on the one end side in the axial direction to a predetermined position further toward the one end side than a center of vane section in the axial direction, the second region spanning from the predetermined position to an edge on the other end side in the axial direction.

Abstract: An optical scanner includes a light source; a light deflector configured to perform scanning in a first scanning direction and a second scanning direction orthogonal to the first scanning direction with irradiation light emitted from the light source; and a screen on which the light deflector performs the scanning with the irradiation light. The optical scanner is configured to turn on the light source based on image information to form an image on the screen in an image area included in a scanning range on the screen. The light deflector is configured to perform the scanning in the scanning range with the irradiation light. The image area has an outer periphery having at least one intersecting side intersecting with both the first scanning direction and the second scanning direction.

Abstract: An artificial shuttlecock feather for implanting in a circular ring shape into a shuttlecock base, including: a vane section and a rachis section having one end in an axial direction of the rachis section fixed to the base and supporting the vane section provided to another end side of the rachis section, a hole being formed in the vane section so as to penetrate the vane section, and a porosity of a first region of the vane section being lower than a porosity of a second region of the vane section, the first region spanning from an edge on the one end side in the axial direction to a predetermined position further toward the one end side than a center of vane section in the axial direction, the second region spanning from the predetermined position to an edge on the other end side in the axial direction.

Abstract: An artificial shuttlecock feather that is to be implanted in a circular ring shape into a base of a shuttlecock, the artificial shuttlecock feather includes: a vane section; and a rachis section having one end in an axial direction of the rachis section fixed to the base and supporting the vane section provided to another end side of the rachis section, a hole being formed in the vane section so as to penetrate the vane section, and a porosity of a first region of the vane section being lower than a porosity of a second region of the vane section, the first region spanning from an edge on the one end side in the axial direction to a predetermined position further toward the one end side than a center of vane section in the axial direction, the second region spanning from the predetermined position to an edge on the other end side in the axial direction.

Abstract: In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Abstract: A signal level adjustment system adjusting a level of signal outputted from a signal output circuit is realized. An input buffer threshold adjustment unit sets a threshold of a signal input circuit to a first variable value. A signal level adjustment unit adjusts an output level of a first signal at the signal output circuit until a voltage of the first signal outputted from the signal output circuit and inputted to the signal input circuit falls into a given range determined based on the threshold.

Abstract: In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Abstract: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Abstract: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Abstract: A parallel process execution method that allocates CPU time to parallel processes at any desired ratios. The method sets a time allocation ratio to determine how much of a given cycle period should be allocated for execution of a parallel program. Process switching is then performed in accordance with the time allocation ratio set to the parallel program. More specifically, parallel processes produced from a parallel program are each assigned to a plurality of processors, and those parallel processes are started simultaneously on the processors. When the time elapsed since the start of the parallel processes has reached a point that corresponds to the time allocation ratio that has been set to the parallel program, the execution of the assigned parallel processes is stopped simultaneously on the plurality of processors.

Abstract: An analog-differential-circuit test device includes transfer gates 13 and 14 for isolating in the test mode an input pair of an analog differential circuit from input nodes IN and INB, a voltage adjusting circuit for generating a voltage pair controlled by a control signal fed from outside of the LSI and input to the input pair during the test mode, and a flip-flop for latching an output from the analog differential circuit. A High-output input characteristic and a Low-output input characteristic of the analog differential circuit itself are measured in the LSI.

Abstract: A signal level adjustment system adjusting a level of signal outputted from a signal output circuit is realized. An input buffer threshold adjustment unit sets a threshold of a signal input circuit to a first variable value. A signal level adjustment unit adjusts an output level of a first signal at the signal output circuit until a voltage of the first signal outputted from the signal output circuit and inputted to the signal input circuit falls into a given range determined based on the threshold.

Abstract: An analog-differential-circuit test device includes transfer gates 13 and 14 for isolating in the test mode an input pair of an analog differential circuit from input nodes IN and INB, a voltage adjusting circuit for generating a voltage pair controlled by a control signal fed from outside of the LSI and input to the input pair during the test mode, and a flip-flop for latching an output from the analog differential circuit. A High-output input characteristic and a Low-output input characteristic of the analog differential circuit itself are measured in the LSI.

Abstract: A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master latch and a slave latch each for temporarily holding an input signal, a first scan controller, a clock controller, and a second scan controller. The first scan controller receives an output signal from the master latch and outputs the received output signal in synchronism with a scan clock which is a clock for testing the semiconductor integrated circuit device, when the semiconductor integrated circuit device is tested. The clock controller receives an output signal from the first scan controller and outputs the received output signal to the slave unit in synchronism with a predetermined clock when in a normal mode of operation.

Abstract: A parallel process execution method that allocates CPU time to parallel processes at any desired ratios. The method sets a time allocation ratio to determine how much of a given cycle period should be allocated for execution of a parallel program. Process switching is then performed in accordance with the time allocation ratio set to the parallel program. More specifically, parallel processes produced from a parallel program are each assigned to a plurality of processors, and those parallel processes are started simultaneously on the processors. When the time elapsed since the start of the parallel processes has reached a point that corresponds to the time allocation ratio that has been set to the parallel program, the execution of the assigned parallel processes is stopped simultaneously on the plurality of processors.

Abstract: A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master latch and a slave latch each for temporarily holding an input signal, a first scan controller, a clock controller, and a second scan controller. The first scan controller receives an output signal from the master latch and outputs the received output signal in synchronism with a scan clock which is a clock for testing the semiconductor integrated circuit device, when the semiconductor integrated circuit device is tested. The clock controller receives an output signal from the first scan controller and outputs the received output signal to the slave unit in synchronism with a predetermined clock when in a normal mode of operation.