Patents by Inventor Yusuke MUKAE
Yusuke MUKAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894298Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.Type: GrantFiled: March 22, 2022Date of Patent: February 6, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
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Publication number: 20230128441Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.Type: ApplicationFiled: October 21, 2021Publication date: April 27, 2023Inventors: Masanori TSUTSUMI, Yusuke MUKAE, Tatsuya HINOUE, Yuki KASAI
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Publication number: 20220352201Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.Type: ApplicationFiled: November 10, 2021Publication date: November 3, 2022Inventors: Tatsuya HINOUE, Yusuke MUKAE, Ryousuke ITOU, Masanori TSUTSUMI, Akio NISHIDA, Ramy Nashed Bassely SAID
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Publication number: 20220352200Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.Type: ApplicationFiled: November 10, 2021Publication date: November 3, 2022Inventors: Michiaki SANO, Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
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Publication number: 20220352199Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.Type: ApplicationFiled: November 10, 2021Publication date: November 3, 2022Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
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Publication number: 20220341877Abstract: A measurement apparatus comprises a memory that stores instructions. The measurement apparatus comprises a processor that executes the instructions stored in the memory to: identify a propagation distance which is a length of a propagation path that a sound wave transmitted from a transmitting apparatus takes before reaching a receiving apparatus; determine, based on the identified propagation distance, a method to be used to identify a propagation time for the sound wave transmitted from the transmitting apparatus to reach the receiving apparatus from among a plurality of methods for identifying a propagation time of a sound wave; identify the propagation time for the sound wave transmitted from the transmitting apparatus to reach the receiving apparatus by the determined method; and measure an air characteristic of a location on the propagation path based on the identified propagation time and the identified propagation distance.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Applicant: Pixie Dust Technologies, Inc.Inventors: Yusuke MUKAE, Yudai TAIRA, Yuki KON, Takumi IINO, Arata TAKAHASHI
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Publication number: 20220216145Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu UEDA
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Patent number: 11377733Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.Type: GrantFiled: August 7, 2020Date of Patent: July 5, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Yusuke Mukae, Naoki Takeguchi
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Patent number: 11289416Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.Type: GrantFiled: November 26, 2019Date of Patent: March 29, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
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Publication number: 20220042171Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.Type: ApplicationFiled: August 7, 2020Publication date: February 10, 2022Inventors: Fei ZHOU, Raghuveer S. MAKALA, Rahul SHARANGPANI, Yusuke MUKAE, Naoki TAKEGUCHI
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Patent number: 11217532Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.Type: GrantFiled: June 27, 2018Date of Patent: January 4, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Tatsuya Hinoue, Tomoyuki Obu, Tomohiro Uno, Yusuke Mukae
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Publication number: 20210159167Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.Type: ApplicationFiled: November 26, 2019Publication date: May 27, 2021Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu Yu UEDA
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Patent number: 10916504Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.Type: GrantFiled: June 14, 2019Date of Patent: February 9, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Yusuke Mukae, Naoki Takeguchi, Kensuke Yamaguchi, Raghuveer S. Makala, Yujin Terasawa
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Publication number: 20200395310Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.Type: ApplicationFiled: June 14, 2019Publication date: December 17, 2020Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Raghuveer S. MAKALA, Yujin TERASAWA
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Patent number: 10615123Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.Type: GrantFiled: June 27, 2018Date of Patent: April 7, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Tatsuya Hinoue, Tomoyuki Obu, Tomohiro Uno, Yusuke Mukae, Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
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Patent number: 10608010Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.Type: GrantFiled: June 7, 2018Date of Patent: March 31, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yujin Terasawa, Genta Mizuno, Yusuke Mukae, Yoshinobu Tanaka, Shiori Kataoka, Ryosuke Itou, Kensuke Yamaguchi, Naoki Takeguchi
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Publication number: 20190287916Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.Type: ApplicationFiled: June 27, 2018Publication date: September 19, 2019Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR, Tatsuya HINOUE, Tomoyuki OBU, Tomohiro UNO, Yusuke MUKAE
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Publication number: 20190287982Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.Type: ApplicationFiled: June 27, 2018Publication date: September 19, 2019Inventors: Tatsuya HINOUE, Tomoyuki OBU, Tomohiro UNO, Yusuke MUKAE, Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR
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Publication number: 20190280001Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.Type: ApplicationFiled: June 7, 2018Publication date: September 12, 2019Inventors: Yujin TERASAWA, Genta MIZUNO, Yusuke MUKAE, Yoshinobu TANAKA, Shiori KATAOKA, Ryosuke ITOU, Kensuke YAMAGUCHI, Naoki TAKEGUCHI
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Publication number: 20170247794Abstract: A process chamber includes multiple partitions within a single continuous vacuum enclosure. Each of the multiple partitions is defined by respective distinct volumes within the single continuous vacuum enclosure that are connected thereamongst for unhindered movement of a substrate therethrough. The multiple partitions are configured to provide different process gases or purge gases to the substrate as the substrate cycles through the multiple positions. The process can cycle through a first deposition step that deposits a first material on the substrate in a first position and a second deposition step that deposits a second material on the substrate in a second position within each cycle. Alternatively or additionally, the process spaces can include at least one precursor treatment space and at least one reaction space.Type: ApplicationFiled: July 26, 2016Publication date: August 31, 2017Inventors: Yusuke MUKAE, Fumitaka AMANO, Naoki TAKEGUCHI