Patents by Inventor Yusuke Nakahashi

Yusuke Nakahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8395447
    Abstract: A low-noise amplifier comprises an input terminal to which a signal is input; a transistor configured to amplify the signal input to the input terminal; an output terminal through which the amplified signal from the transistor is output; a feedback amount regulator circuit configured to regulate an amplitude of the signal output from the transistor as a feedback amount and output a voltage; a bias circuit configured to generate a bias current fed to the transistor; a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed; a first input bias circuit configured to generate th
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Yusuke Nakahashi, Naoki Okamoto
  • Publication number: 20120154047
    Abstract: A low-noise amplifier comprises an input terminal to which a signal is input; a transistor configured to amplify the signal input to the input terminal; an output terminal through which the amplified signal from the transistor is output; a feedback amount regulator circuit configured to regulate an amplitude of the signal output from the transistor as a feedback amount and output a voltage; a bias circuit configured to generate a bias current fed to the transistor; a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed; a first input bias circuit configured to generate th
    Type: Application
    Filed: July 8, 2011
    Publication date: June 21, 2012
    Inventors: Yusuke NAKAHASHI, Naoki OKAMOTO
  • Publication number: 20080261651
    Abstract: In a multi-mode communication apparatus including independent transmitter circuits and receiver circuits of a W-CDMA system and a GSM system, which are capable of complying with communication systems of the W-CDMA system and the GSM system, a first switching device is connected between a ground and an input terminal of a first low-noise amplifier of the receiver circuit of the W-CDMA communication system, and is selectively turned on and off in accordance with a first control signal. A second switching device is connected between the ground and an input terminal of a second low-noise amplifier of the receiver circuit of the GSM communication system, and is selectively turned on and off in accordance with a second control signal. A control circuit generates and outputs first and second control signals for controlling turning-on and -off of the first and second switching devices, respectively.
    Type: Application
    Filed: January 15, 2008
    Publication date: October 23, 2008
    Inventors: Yusuke NAKAHASHI, Naoki OKAMOTO, Junji ITO