Patents by Inventor Yusuke Nakanishi

Yusuke Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155192
    Abstract: A control device includes: an obtainer that obtains content and first type information indicating a type of the content; a determiner that performs type determination processing on the content obtained by obtainer, to obtain second type information indicating a type of the content; and a generator that generates and outputs control information for increasing intensity of a presentation effect to be applied at a time of presentation of the content when the first type information and the second type information match, compared to when the first type information and the second type information do not match.
    Type: Application
    Filed: October 8, 2021
    Publication date: May 9, 2024
    Inventors: Hisashi ICHIMIYA, Yusuke MAEKAWA, Hideo NAKANISHI
  • Publication number: 20240124407
    Abstract: A compound represented by the following general formula (B1). Further disclosed is a corrosion inhibitor (B) containing one or more selected from the compound represented by the following formula (B1). Further disclosed is a lubricant composition containing an ionic liquid (A) and the corrosion inhibitor (B). The compound and the corrosion inhibitor are excellent in stability in any of a high vacuum, a low-temperature environment, a high-temperature environment, and an ordinary temperature-ordinary pressure environment, and the lubricant composition containing the corrosion inhibitor is excellent in metal corrosion resistance, solubility, and low evaporability. In the general formula (B1), M is an alkali metal and RB11 is an alkylene group having 1 to 19 carbon atoms.
    Type: Application
    Filed: December 24, 2021
    Publication date: April 18, 2024
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Yukio YOSHIDA, Yusuke NAKANISHI, Hideaki HATTORI
  • Publication number: 20240121530
    Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Inventors: Tatsuya KABE, Hideyuki ARAI, Hisashi AIKAWA, Yuki SUGIURA, Akito INOUE, Mitsuyoshi MORI, Kentaro NAKANISHI, Yusuke SAKATA
  • Patent number: 11948958
    Abstract: The solid-state imaging element includes a photoelectric converter, a first separator, and a second separator. The photoelectric converter is configured to perform photoelectric conversion of incident light. The first separator configured to separate the photoelectric converter is formed in a first trench formed from a first surface side. The second separator configured to separate the photoelectric converter is formed in a second trench formed from a second surface side facing a first surface. The present technology is applicable to an individual imaging element mounted on, e.g., a camera and configured to acquire an image of an object.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 2, 2024
    Assignee: SONY GROUP CORPORATION
    Inventors: Hideyuki Honda, Tetsuya Uchida, Toshifumi Wakano, Yusuke Tanaka, Yoshiharu Kudoh, Hirotoshi Nomura, Tomoyuki Hirano, Shinichi Yoshida, Yoichi Ueda, Kosuke Nakanishi
  • Publication number: 20230365885
    Abstract: A complex including an active ingredient, and a surfactant. The active ingredient is one or more less-oil-soluble substances selected from the group consisting of a hardly-oil-soluble substance and an oil-insoluble substance, and the one or more less-oil-soluble substances function as an additive for lubricating oil. A method of making the complex.
    Type: Application
    Filed: September 30, 2021
    Publication date: November 16, 2023
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Hiroaki KOSHIMA, Yusuke NAKANISHI
  • Patent number: 11542453
    Abstract: The present invention addresses a problem of providing a grease composition that uses hydrophilic nanofibers but still has excellent water resistance and does not readily experience oil separation. The grease composition contains a base oil, hydrophilic nanofibers having a thickness (d) of 1 to 500 nm, and an organic bentonite.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 3, 2023
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Yusuke Nakanishi, Hiromu Kumagai
  • Patent number: 11474047
    Abstract: A non-transitory computer-readable recording medium recording an image processing program that causes a computer to execute processing of: specifying a damaged portion by analyzing a captured image of a construction; and predicting, in the captured image, a range to which damage spreads based on the specified damaged portion and design data associated with the construction.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 18, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yusuke Nakanishi, Hideyuki Kikuchi, Hiroshi Yamagami
  • Patent number: 11343515
    Abstract: A computer-readable recording medium storing a program that causes a computer to execute a process, the process includes specifying occurrence frequencies of respective gradation values with regard to pixels included in image data and represented by gradation values of a predetermined bit count; extracting a predetermined number of gradation values from a gradation value having a high occurrence frequency in a descending order; generating correspondence information for performing bit conversion of the extracted gradation values into coded values of a bit count in accordance with the predetermined number; and encoding the image data by performing bit conversion of first pixels having any one of the predetermined number of gradation values among the pixels based on the correspondence information, and performing bit conversion of second pixels having any one of gradation values other than the predetermined number of gradation values among the pixels.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 24, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Koichi Oikawa, Hideyuki Kikuchi, Yusuke Nakanishi
  • Publication number: 20220145207
    Abstract: The present invention addresses a problem of providing a grease composition for a speed reducer and a speed increaser, excellent in both leakage prevention performance and energy transfer efficiency. The grease composition for a speed reducer and a speed increaser contains a base oil (A), and nanofibers (B) having a thickness (d) of 1 to 500 nm, wherein the nanofibers (B) are one or more selected from cellulose nanofibers (B1) and modified cellulose nanofibers (B2).
    Type: Application
    Filed: February 27, 2020
    Publication date: May 12, 2022
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventor: Yusuke NAKANISHI
  • Patent number: 11145045
    Abstract: An image processing method is performed by a computer, for determining that a line is a crack or something other than the crack. The method includes: extracting a linear region from an image of an object captured by an imaging apparatus; determining a luminosity change in a direction traversing the linear region at each of a plurality of positions separate in a longitudinal direction of the linear region; and identifying a type of the linear region based on the luminosity changes at the plurality of positions.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Yusuke Nakanishi, Hideyuki Kikuchi, Koichi Oikawa
  • Patent number: 10959361
    Abstract: Movable section of a cut and clinch unit includes exchange section in which is formed second insertion hole for cutting and bending a lead, and main body section to which exchange section is removably attached. An opening position of the second insertion hole is calculated as an attachment position of the exchange section on the main body section based on image data. It is determined whether a difference between the calculated opening position and a standard position of the second insertion hole that is set in advance exceeds a threshold value. If the difference between the calculated opening position and the standard position exceeds the threshold value, calibration is performed based on the assumption that the exchange section has been exchanged.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 23, 2021
    Assignee: FUJI CORPORATION
    Inventor: Yusuke Nakanishi
  • Publication number: 20210082954
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
  • Publication number: 20210009916
    Abstract: The present invention addresses a problem of providing a grease composition that uses hydrophilic nanofibers but still has excellent water resistance and does not readily experience oil separation. The grease composition contains a base oil, hydrophilic nanofibers having a thickness (d) of 1 to 500 nm, and an organic bentonite.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 14, 2021
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Yusuke NAKANISHI, Hiromu KUMAGAI
  • Patent number: 10829711
    Abstract: Provided is a grease containing a base oil and a hydrophilic nanofiber, the hydrophilic nanofiber having a thickness (d) of 0.01 to 500 nm being dispersed therein. The grease is low in an environmental load and excellent in safety on the human body and also has an appropriate worked penetration and has a high dropping point, and therefore, it is also excellent in heat resistance.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 10, 2020
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Yusuke Nakanishi, Hiromu Kumagai
  • Publication number: 20200300779
    Abstract: A non-transitory computer-readable recording medium recording an image processing program that causes a computer to execute processing of: specifying a damaged portion by analyzing a captured image of a construction; and predicting, in the captured image, a range to which damage spreads based on the specified damaged portion and design data associated with the construction.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Nakanishi, Hideyuki Kikuchi, Hiroshi YAMAGAMI
  • Publication number: 20200252633
    Abstract: A computer-readable recording medium storing a program that causes a computer to execute a process, the process includes specifying occurrence frequencies of respective gradation values with regard to pixels included in image data and represented by gradation values of a predetermined bit count; extracting a predetermined number of gradation values from a gradation value having a high occurrence frequency in a descending order; generating correspondence information for performing bit conversion of the extracted gradation values into coded values of a bit count in accordance with the predetermined number; and encoding the image data by performing bit conversion of first pixels having any one of the predetermined number of gradation values among the pixels based on the correspondence information, and performing bit conversion of second pixels having any one of gradation values other than the predetermined number of gradation values among the pixels.
    Type: Application
    Filed: January 22, 2020
    Publication date: August 6, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Koichi OIKAWA, Hideyuki Kikuchi, Yusuke Nakanishi
  • Publication number: 20200212066
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
  • Patent number: 10600803
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Nakanishi, Takaya Yamanaka, Akira Matsumura
  • Publication number: 20190385295
    Abstract: An image processing method is performed by a computer, for determining that a line is a crack or something other than the crack. The method includes: extracting a linear region from an image of an object captured by an imaging apparatus; determining a luminosity change in a direction traversing the linear region at each of a plurality of positions separate in a longitudinal direction of the linear region; and identifying a type of the linear region based on the luminosity changes at the plurality of positions.
    Type: Application
    Filed: May 20, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Nakanishi, Hideyuki Kikuchi, Koichi OIKAWA
  • Publication number: 20190283288
    Abstract: Provided is a foamed heat-insulating material which encapsulates therein a low-heat conductivity gas and which yields high heat insulating performance. High-melting point beads that have been foamed up to a prescribed expansion ratio with a gas of low thermal conductivity by using a resin that does not soften at the beads-foaming temperature and that has a low gas transmission rate are mixed with low-temperature foam beads to be foamed within a forming die, and the resultant mixture is filled in a beads forming die cavity and foamed by heating.
    Type: Application
    Filed: November 22, 2017
    Publication date: September 19, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yusuke NAKANISHI, Yuta KUBO, Masaru IMAIZUMI, Kazushi KONO