Patents by Inventor Yusuke Natsui

Yusuke Natsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240428080
    Abstract: According to one embodiment, an information processing device includes a target model learning unit, a change unit, a selection unit, and a student model learning unit. The target model learning unit learns a target model to be subjected to size reduction. The change unit changes the target model into a student model with a size smaller than a size of the target model. The selection unit selects, as a teacher model, one of a plurality of models including the target model and one or more intermediate models with a size smaller than the size of the target model in accordance with a comparison result between the size of the target model and the size of the student model. The student model learning unit learns the student model by distillation using the selected teacher model.
    Type: Application
    Filed: February 27, 2024
    Publication date: December 26, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusuke NATSUI
  • Publication number: 20240028901
    Abstract: According to one embodiment, a learning apparatus includes a processor. The processor performs, on a neural network model, an adaptation processing that includes at least either insertion of an activation function, or correction of the activation function. The processor generates a trained model by training the neural network model on which the adaptation processing has been performed. The processor performs pruning on the trained model to generate a reconstructed model from which a parameter has been reduced.
    Type: Application
    Filed: February 22, 2023
    Publication date: January 25, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Albert RODRIGUEZ MULET, Shuhei NITTA, Yoshiyuki KOKOJIMA, Ryusuke HIRAI, Yasutaka FURUSHO, Manabu NISHIYAMA, Yusuke NATSUI
  • Publication number: 20230186092
    Abstract: A learning device according to one embodiment includes one or more hardware processors. The one or more hardware processors function as an output control unit, a receiving unit, and a training unit. The output control unit serves to output pieces of model information including respective accuracy and performance of learning models with different sizes. The receiving unit serves to receive input made by a user. The training unit serves to train one of the learning models represented by one of the pieces of model information selected by the user.
    Type: Application
    Filed: August 26, 2022
    Publication date: June 15, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusuke NATSUI
  • Patent number: 11604717
    Abstract: A processor performance measurement apparatus according to an embodiment includes a processor, in which the processor detects that a memory access occurs, the memory access being required to execute processing units or execute execution units by a processor to be measured, performs first estimation for estimating switching of the processing units or the execution units and second estimation for estimating which of the one or more processing units the processing unit being executed is or to which of the one or more processing units the execution unit being executed corresponds based on an address of an access destination of the memory access, measures respective performances in the processing units or the execution units based on an estimation result of the first estimation, and aggregates respective measurement results of the performances for each of the processing units based on an estimation result of the second estimation.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 14, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yusuke Natsui
  • Publication number: 20220092385
    Abstract: An Information processing device includes one or more memories and one or more processing circuitry. The one or more memories are configured to store information that identifies hardware, information that identifies a deep neural network (DNN) structure, and an execution time when the hardware executes the DNN structure. The one or more processing circuitry is configured to search for whether a combination of target hardware and a target DNN structure is stored in the memories, and acquire the execution time from a combination of the target hardware and the target DNN structure based on a search result of the search unit.
    Type: Application
    Filed: March 16, 2021
    Publication date: March 24, 2022
    Inventor: Yusuke NATSUI
  • Publication number: 20210286700
    Abstract: A processor performance measurement apparatus according to an embodiment includes a processor, in which the processor detects that a memory access occurs, the memory access being required to execute processing units or execute execution units by a processor to be measured, performs first estimation for estimating switching of the processing units or the execution units and second estimation for estimating which of the one or more processing units the processing unit being executed is or to which of the one or more processing units the execution unit being executed corresponds based on an address of an access destination of the memory access, measures respective performances in the processing units or the execution units based on an estimation result of the first estimation, and aggregates respective measurement results of the performances for each of the processing units based on an estimation result of the second estimation.
    Type: Application
    Filed: August 31, 2020
    Publication date: September 16, 2021
    Inventor: Yusuke Natsui