Patents by Inventor Yusuke Nitta

Yusuke Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 6867632
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yusuke Nitta, Toshihiro Hattori
  • Semiconductor integrated circuit device
    Publication number: 20040036518
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Application
    Filed: August 27, 2003
    Publication date: February 26, 2004
    Inventors: Yusuke Nitta, Toshihiro Hattori
  • Semiconductor integrated circuit device
    Patent number: 6636095
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Nitta, Toshihiro Hattori
  • Semiconductor integrated circuit device
    Publication number: 20030006819
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Application
    Filed: September 11, 2002
    Publication date: January 9, 2003
    Inventors: Yusuke Nitta, Toshihiro Hattori
  • Semiconductor integrated circuit device
    Patent number: 6462599
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Nitta, Toshihiro Hattori
  • Semiconductor integrated circuit device
    Publication number: 20010028265
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Application
    Filed: May 22, 2001
    Publication date: October 11, 2001
    Inventor: Yusuke Nitta
  • Semiconductor integrated circuit device
    Patent number: 6246277
    Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: June 12, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Nitta, Toshihiro Hattori