Abstract: An optical signal detection circuit (10) includes an amplification circuit (11) that differentially amplifies an electrical signal (Tout) corresponding to the pulse train of an optical signal (Pin) and outputs a differential output signal (Aout), and a comparator (12) that compares the voltage value of the positive-phase signal of the differential output signal (Aout) with the voltage value of the negative-phase signal and outputs a pulsed comparison output signal (Cout) corresponding to the comparison result. The amplification circuit (11) includes a current addition circuit (11E) that adjusts a DC load current to generate a positive-phase signal (Aout+) and a negative-phase signal (Aout?) of the differential output signal (Aout) in accordance with an adjusted voltage value from an external adjusted voltage source (Vadj) and adjusts the DC bias of the positive-phase signal (Aout+) and the DC bias of the negative-phase signal (Aout?).

Abstract: An inductor (1) includes an inductor (L11P) formed into the shape of a spiral on the outer circumference of an inductor region and having a start point connected to a terminal (N11P), an inductor (L12P) formed into the shape of a spiral on the inner circumference of the inductor region and having a start point at the end point of the inductor (L11P) and an end point connected to a terminal (N12P), and an inductor (L13P) formed into the shape of a spiral in a region sandwiched between the inductor (L11P) and the inductor (L12P) and having a start point at a node between the inductor (L11P) and the inductor (L12P) and an end point connected to a terminal (N13P).

Abstract: A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).

Abstract: An inductor (1) includes an inductor (L11P) formed into the shape of a spiral on the outer circumference of an inductor region and having a start point connected to a terminal (N11P), an inductor (L12P) formed into the shape of a spiral on the inner circumference of the inductor region and having a start point at the end point of the inductor (L11P) and an end point connected to a terminal (N12P), and an inductor (L13P) formed into the shape of a spiral in a region sandwiched between the inductor (L11P) and the inductor (L12P) and having a start point at a node between the inductor (L11P) and the inductor (L12P) and an end point connected to a terminal (N13P).

Abstract: A recovered clock (123) is generated by making the phase of a reference clock (122) having the same frequency as the data rate frequency of input data (120) match the phase of the input data (120). The input data (120) is written in a FIFO (101) using the recovered clock (123). For readout from the FIFO (101), the FIFO (101) is caused to output recovered data (121) using the reference clock (122) asynchronous to the recovered clock (123).

Abstract: An optical signal detection circuit (10) includes an amplification circuit (11) that differentially amplifies an electrical signal (Tout) corresponding to the pulse train of an optical signal (Pin) and outputs a differential output signal (Aout), and a comparator (12) that compares the voltage value of the positive-phase signal of the differential output signal (Aout) with the voltage value of the negative-phase signal and outputs a pulsed comparison output signal (Cout) corresponding to the comparison result. The amplification circuit (11) includes a current addition circuit (11E) that adjusts a DC load current to generate a positive-phase signal (Aout+) and a negative-phase signal (Aout?) of the differential output signal (Aout) in accordance with an adjusted voltage value from an external adjusted voltage source (Vadj) and adjusts the DC bias of the positive-phase signal (Aout+) and the DC bias of the negative-phase signal (Aout?).

Abstract: A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).

Abstract: A clock/data recovery circuit includes a data duty correction circuit which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit which generates a recovered clock in synchronism with the edge timing of the corrected data, a data decision circuit which performs data decision of the corrected data based on the recovered clock, and a data duty detection circuit which detects the duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to the data duty correction circuit.

Abstract: A recovered clock (123) is generated by making the phase of a reference clock (122) having the same frequency as the data rate frequency of input data (120) match the phase of the input data (120). The input data (120) is written in a FIFO (101) using the recovered clock (123). For readout from the FIFO (101), the FIFO (101) is caused to output recovered data (121) using the reference clock (122) asynchronous to the recovered clock (123).

Abstract: A clock/data recovery circuit includes a data duty correction circuit (400) which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit (100) which generates a recovered clock in synchronism with the edge timing of the corrected data, a data decision circuit (200) which performs data decision of the corrected data based on the recovered clock, and a data duty detection circuit (300) which detects the duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to the data duty correction circuit.