Patents by Inventor Yusuke OJIMA

Yusuke OJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290879
    Abstract: A performance of a semiconductor device including a main MOSFET and a sensing MOSFET having a double-gate structure including a gate electrode and a field plate electrode inside a trench is improved. A main MOSFET including a gate electrode and a field plate electrode inside a second trench and a sensing MOSFET for electric-current detection including a gate electrode and a field plate electrode inside a fourth trench are surrounded by different termination rings, respectively.
    Type: Application
    Filed: December 13, 2022
    Publication date: September 14, 2023
    Inventors: Seiji HIRABAYASHI, Yusuke OJIMA
  • Publication number: 20230253398
    Abstract: A semiconductor device includes a first power semiconductor device, a first Nch MOSFET whose drain is coupled to a gate of the first power semiconductor device, a first gate resistor coupled to a source of the first Nch MOSFET and a first diode coupled between the source and drain of the first Nch MOSFET.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Inventor: Yusuke OJIMA
  • Patent number: 11493542
    Abstract: A semiconductor device includes m power transistors (m is an integer of 2 or more) coupled in parallel each of which has a sense source terminal, a Kelvin terminal and a source terminal, a first average circuit that connects the first resistor and the second resistor in order between the sense source terminal and the Kelvin terminal and generates first to fourth average voltages and an arithmetic circuit that measures a first current value flowing through the sense source terminal from the first and second average voltages, measures a second current value flowing through the sense source terminal from the third and fourth average voltages and measures a current value flowing through the source terminal from the first to fourth average voltages and the first and second current values.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 8, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiko Yokoi, Yusuke Ojima
  • Patent number: 11373941
    Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 28, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshimasa Uchinuma, Yusuke Ojima
  • Publication number: 20220115306
    Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 14, 2022
    Inventors: Yoshimasa UCHINUMA, Yusuke OJIMA
  • Publication number: 20210141006
    Abstract: A semiconductor device includes m power transistors (m is an integer of 2 or more) coupled in parallel each of which has a sense source terminal, a Kelvin terminal and a source terminal, a first average circuit that connects the first resistor and the second resistor in order between the sense source terminal and the Kelvin terminal and generates first to fourth average voltages and an arithmetic circuit that measures a first current value flowing through the sense source terminal from the first and second average voltages, measures a second current value flowing through the sense source terminal from the third and fourth average voltages and measures a current value flowing through the source terminal from the first to fourth average voltages and the first and second current values.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 13, 2021
    Inventors: Yoshihiko YOKOI, Yusuke OJIMA
  • Patent number: 10305412
    Abstract: In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Ojima, Yoshihiko Yokoi
  • Publication number: 20180351475
    Abstract: A power conversion system includes a high-side circuit and a low-side circuit, a controller communicating with the high-side circuit and the low-side circuit; a first coupling circuit including a wire between the controller and the high-side circuit; and a second coupling circuit including a wire between the controller and the low-side circuit.
    Type: Application
    Filed: July 19, 2018
    Publication date: December 6, 2018
    Inventors: Yoshihiko YOKOI, Yusuke OJIMA, Koichi YAMAZAKI
  • Patent number: 10115652
    Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.
    Type: Grant
    Filed: February 11, 2017
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Numabe, Koji Tateno, Yusuke Ojima, Yoshihiko Yokoi, Shinya Ishida, Hitoshi Matsuura
  • Patent number: 10116292
    Abstract: There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiko Yokoi, Yusuke Ojima
  • Patent number: 10069439
    Abstract: A power conversion system has a first coupling circuit including a wire between a controller and a high-side circuit and a second coupling circuit including a wire between the controller and a low-side circuit. The first coupling circuit has a diode having an anode coupled to a wire from the controller and a cathode coupled to a wire from the high-side circuit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiko Yokoi, Yusuke Ojima, Koichi Yamazaki
  • Publication number: 20180183433
    Abstract: To provide a semiconductor device capable of preventing a surge voltage at the time of turn-off without complicating a gate drive circuit and without increasing switching delay. A semiconductor device has a configuration in which a plurality of transistors are equivalently coupled in parallel by including a plurality of control electrodes for controlling a current flowing between a first main electrode and a second main electrode. A resistance value of a transmission path of a control signal from a common control terminal varies with respect to each of the control electrodes.
    Type: Application
    Filed: November 15, 2017
    Publication date: June 28, 2018
    Inventors: Yusuke OJIMA, Yoshihiko YOKOI
  • Publication number: 20170288653
    Abstract: There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.
    Type: Application
    Filed: March 24, 2017
    Publication date: October 5, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshihiko YOKOI, Yusuke OJIMA
  • Publication number: 20170288597
    Abstract: In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.
    Type: Application
    Filed: February 14, 2017
    Publication date: October 5, 2017
    Inventors: Yusuke OJIMA, Yoshihiko YOKOI
  • Publication number: 20170287802
    Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.
    Type: Application
    Filed: February 11, 2017
    Publication date: October 5, 2017
    Inventors: Hideo NUMABE, Koji TATENO, Yusuke OJIMA, Yoshihiko YOKOI, Shinya ISHIDA, Hitoshi MATSUURA
  • Publication number: 20170179849
    Abstract: A power conversion system has a first coupling circuit including a wire between a controller and a high-side circuit and a second coupling circuit including a wire between the controller and a low-side circuit. The first coupling circuit has a diode having an anode coupled to a wire from the controller and a cathode coupled to a wire from the high-side circuit.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 22, 2017
    Inventors: Yoshihiko YOKOI, Yusuke OJIMA, Koichi YAMAZAKI