Abstract: Some embodiments include a semiconductor device having two gate electrodes which are of about a same gate width as one another, and having a first diffusion region between the two gate electrodes. The semiconductor device also has second and third diffusion regions on opposing sides of the two gate electrodes from one another and which sandwich the two gate electrodes and the first source/drain region therebetween. Each of the second and third diffusion regions is longer than the first diffusion region in a direction of the gate width. Some embodiments include a semiconductor device having a PMOS construction and an NMOS construction, with both constructions having a shorter middle diffusion region sandwiched between a pair of longer outer diffusion regions.