Abstract: The present invention is provided with an embedded system (100) capable of performing control without any malfunction is provided, by including processing circuitry configured to: start a reading process; assign a read identification (ID) for each reading process, and to update a read ID number indicating the number of assigned read IDs; read communication data; and acquire, upon finishing a read process, a data writing-in-progress flag indicating whether a writing process is being performed, and a writing time identification (ID) number indicating the read ID number at the time of a data writing process, and to judge the consistency of the read data read, based on the data writing-in-progress flag, the read IDs, and a writing time read ID number.

Abstract: The present invention is provided with an embedded system capable of performing control without any malfunction is provided, by including a read start means to start a reading process, a read matching start means to assign a read ID for each reading process, and to update a read ID number indicating the number of read IDs assigned, a reading means to read communication data, a read finish means to finish reading by the reading means, and a read matching finish means to acquire a data writing-in-progress flag indicating whether a writing process is being performed, and a writing time ID number indicating the read ID number at the time of a data writing process, and to judge consistency of data read, based on the data writing-in-progress flag, the read IDs, and a writing time read ID number.

Abstract: An LSI includes an address decoder in which combinations of IP cores and control registers simultaneously accessed according to an operation mode signal are set in advance, so that the plurality of control registers can be accessed with a single system address signal. Therefore, it is unnecessary that the CPU is provided with selection signals whose number is equal to that of the combinations of the control registers. This reduces coding work for operating CPU, reducing work in developing a program of the CPU.

Abstract: An LSI includes an address decoder in which combinations of IP cores and control registers simultaneously accessed according to an operation mode signal are set in advance, so that the plurality of control registers can be accessed with a single system address signal. Therefore, it is unnecessary that the CPU is provided with selection signals whose number is equal to that of the combinations of the control registers. This reduces coding work for operating CPU, reducing work in developing a program of the CPU.

Abstract: A simulation apparatus performs a simulation of a program for executing a plurality of instructions included in an instruction set of a processor. A bus model unit accepts an access request to a memory storing the program, performs arbitration for a bus, and calculates a cycle count of the processor until use of the bus is granted, for each instruction of the program. A cycle count accumulation unit computes a cycle count required for executing the program based on the cycle count for each instruction calculated by the bus model unit.