Patents by Inventor Yusuke Shirota

Yusuke Shirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150262715
    Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 17, 2015
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
  • Patent number: 9110667
    Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
  • Publication number: 20150228047
    Abstract: A data processing device according to embodiments may comprise: a processor that reconstructs a plurality of update requests for updating at least a part of a display into one or more update requests, or determine that the plurality of the update requests are unnecessary; and an update instruction unit that instructs to execute update processes of the display using the reconstructed one or more update requests.
    Type: Application
    Filed: February 6, 2015
    Publication date: August 13, 2015
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Akihiro Shibata
  • Publication number: 20150212572
    Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.
    Type: Application
    Filed: April 13, 2015
    Publication date: July 30, 2015
    Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
  • Patent number: 9043631
    Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
  • Publication number: 20150089261
    Abstract: According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 26, 2015
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Haruhiko Toyama
  • Publication number: 20150084892
    Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 26, 2015
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
  • Publication number: 20140240333
    Abstract: A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Shiyo Yoshimura
  • Publication number: 20140245047
    Abstract: According to an embodiment, an information processing apparatus that includes a processor, has a first control unit, a power storage unit, and a second control unit. The first control unit is configured to control execution of a process by the processor. The power storage unit is configured to store therein power. The second control unit is configured to control reduction of power consumption of the information processing apparatus in a case where there is a process waiting to be executed and an amount of stored power of the power storage unit is equal to or less than a first threshold.
    Type: Application
    Filed: December 30, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shiyo Yoshimura, Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
  • Publication number: 20140245045
    Abstract: According to an embodiment, a control device includes a processor setting unit, a resumption data reading unit, and a resumption processing unit. The processor setting unit is configured to identify, among a plurality of processors included in an information processing system, each of which is connected to one or more memories, a processor connected to a memory storing resumption data for resuming the information processing system and to activate the identified processor, in response to a resumption request for resuming the information processing system from hibernation. The information processing system includes two or more processors each connected with one or more memories. The resumption data reading unit is configured to read the resumption data from the memory that stores the resumption data. The resumption processing unit is configured to resume the information processing system by using the read resumption data.
    Type: Application
    Filed: December 10, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi Haruki, Masaya Tarui, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Haruhiko Toyama
  • Publication number: 20140245039
    Abstract: According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Shiyo Yoshimura, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
  • Publication number: 20140089715
    Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
  • Publication number: 20140075227
    Abstract: A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
  • Publication number: 20140013138
    Abstract: According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.
    Type: Application
    Filed: March 6, 2013
    Publication date: January 9, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Akihiro Shibata, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Hiroyoshi Haruki, Haruhiko Toyama
  • Publication number: 20140013140
    Abstract: According to an embodiment, an information processing apparatus includes a processor, a first memory, and a power supply controller. The processor is configured to execute a program. The first memory is configured to store therein the program. The power supply controller is configured to stop supplying a power to the first memory when the processor transitions to an idle state where the processor waits for an interrupt, and start supplying the power to the first memory when the processor receives the interrupt in the idle state. When the processor receives the interrupt in the idle state, the processor executes initialization of the first memory to set the first memory into a state where the first memory is accessible from the processor.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 9, 2014
    Inventors: Junichi Segawa, Tatsunori Kanai, Koichi Fujisaki, Tetsuro Kimura, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata
  • Publication number: 20130268781
    Abstract: According to an embodiment, a state control device controls a state transition of an information processing device. The information processing device includes a processor; a power supply unit; and an electric storage unit. The state control device includes a controller to, when the power amount accumulated in the electric storage unit is decreased to a first power amount while the information processing device is in a first state, cause the information processing device to transit from the first state to a second state in which power consumption of the processor is lower than that in the first state, and to, when the power amount accumulated in the electric storage unit is increased to a second power amount larger than the first power amount while the information processing device is in the second state, cause the information processing device to transit from the second state to the first state.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 10, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Akihiro Shibata, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Hiroyoshi Haruki, Haruhiko Toyama
  • Publication number: 20130254773
    Abstract: According to an embodiment, a control apparatus for controlling a target device includes an estimation unit and an issuing unit. The estimation unit is configured to estimate a second amount of energy required for the entire system including the target device and the control apparatus until the target device completes an execution of its function that is requested in accordance with an execution request for the target device. The issuing unit is configured to issue a control command for causing the target device to execute its function in accordance with the execution request, when the first amount of energy at a time point of receiving the execution request is greater than the second amount of energy.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
  • Publication number: 20130191670
    Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
    Type: Application
    Filed: December 21, 2012
    Publication date: July 25, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
  • Publication number: 20130080812
    Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.
    Type: Application
    Filed: July 11, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke SHIROTA, Tetsuro KIMURA, Tatsunori KANAI, Haruhiko TOYAMA, Koichi FUJISAKI, Junichi SEGAWA, Masaya TARUI, Satoshi SHIRAI, Hiroyoshi HARUKI, Akihiro SHIBATA
  • Publication number: 20130080813
    Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.
    Type: Application
    Filed: July 24, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata