Abstract: A three-dimensional structure according to an embodiment of the present disclosure includes: a plurality of resin layers including a light curable resin, the light curable resin including a coloring compound, a color developing-reducing agent, and a photothermal conversion agent, the plurality of resin layers being stacked, the color developing-reducing agent having an average particle diameter of 10 ?m or more and 100 ?m or less.

Abstract: A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.

Abstract: A product design system includes a first transmitting section that uses a look-up table to convert second design image data for which image correction is completed into third design image data of a color space that is represented with a thermochromic material, and transmits the third design image data derived from the conversion to an external apparatus, and a second transmitting section that transmits a decorating request based on fourth design image data that is profile-transformed from the second design image data to a decorating apparatus.

Abstract: A piston of an internal combustion engine configured to be reciprocable along an axial direction in a cylinder includes a cavity formed to be recessed in a center of a piston top surface, and an outer circumferential edge portion located on a radially outer side of the cavity in the piston top surface. The cavity includes a lip portion which has an inclined surface extending obliquely downward from the outer circumferential edge portion toward a radially inner side, a raised portion protruding upward from a bottom of the cavity, and a curved portion connecting the raised portion and the lip portion.

Abstract: A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.

Abstract: A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.

Abstract: A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.

Abstract: A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node; a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied; a second transistor having a source to which a first voltage is to be applied, a drain coupled to the third node, and a gate coupled to a first predetermined node being one of the first node and the second node; a third transistor having a source to which a second voltage is to be applied, a drain coupled to the third node, and a gate coupled to a second predetermined node being the other of the first node and the second node; and a driver.

Abstract: A semiconductor circuit according to the disclosure includes a first circuit that can generate an inverted voltage of a voltage at a first-node and apply the inverted voltage to a second-node, a second circuit that can generate an inverted voltage of the voltage at the second-node and apply the inverted voltage to the first-node, a first transistor coupling the first-node to the third-node by turning on, a first storage element having a first terminal coupled to the third-node and a second terminal supplied with a control voltage and being able to take a first or second resistance state, a first voltage setting circuit that is coupled to the third-node and can set a voltage at the third-node to a voltage corresponding to a voltage at a predetermined node out of the first and second nodes, and a driver controlling an operation of the first transistor and setting the control voltage.

Abstract: [Problem] Provided are a semiconductor device and a multiply-accumulate operation device that enable integration at a higher density by further reducing a mounting area per synapse. [Solution] A semiconductor device including: a plurality of synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series; and an output line that outputs a sum of currents flowing through the plurality of synapses. [Selected Drawing] FIG.

Abstract: To provide a product-sum calculation device and a product-sum calculation method capable of more efficient operation. A product-sum calculation device includes: a plurality of synapses including a transistor and having a variable resistance value; a plurality of input lines extending in a first direction and configured to propagate an input signal to each of the plurality of synapses; a plurality of output lines extending in a second direction orthogonal to the first direction, and configured to output a product-sum calculation result of the input signal from each of the plurality of synapses; and a charge and discharge control unit configured to control an output state of the product-sum calculation result by controlling a charge and discharge state of the output line on the basis of a polarity of the transistor.

Abstract: A semiconductor circuit according to the disclosure includes a first circuit that can generate an inverted voltage of a voltage at a first-node and apply the inverted voltage to a second-node, a second circuit that can generate an inverted voltage of the voltage at the second-node and apply the inverted voltage to the first-node, a first transistor coupling the first-node to the third-node by turning on, a first storage element having a first terminal coupled to the third-node and a second terminal supplied with a control voltage and being able to take a first or second resistance state, a first voltage setting circuit that is coupled to the third-node and can set a voltage at the third-node to a voltage corresponding to a voltage at a predetermined node out of the first and second nodes, and a driver controlling an operation of the first transistor and setting the control voltage.

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.