Patents by Inventor Yusuke Takeuchi

Yusuke Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8073166
    Abstract: While a dielectric film is set to have a ground potential, a fixed electrode is set to have a different potential from the ground potential. Thereafter, ions produced by corona discharge are allowed to pass through a plurality of acoustic holes formed in the fixed electrode and reach the dielectric film, thereby electretizing the dielectric film.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: December 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Yusuke Takeuchi, Hiroshi Ogura
  • Patent number: 8065919
    Abstract: A MEMS device includes: a substrate having a through hole; a first film provided on a top surface of the substrate with a bottom surface of the first film exposed in the through hole; a second film provided over the first film with an air gap interposed therebetween, and having a hole grouping including holes each in communication with the air gap; and a supporting layer interposed between the first and second films and having the air gap formed therein. Outermost holes of the hole grouping are located at regular intervals along a shape of an opening of the through hole at an upper open end.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: November 29, 2011
    Assignee: Panasonic Corporation
    Inventor: Yusuke Takeuchi
  • Publication number: 20110215672
    Abstract: A MEMS device includes: a semiconductor substrate; a vibrating film formed on the semiconductor substrate with a restraining portion interposed between the vibrating film and the semiconductor substrate, and including a lower electrode, and a fixed film formed on the semiconductor substrate with a support portion interposed between the fixed film and the semiconductor substrate to cover the vibrating film, and including an upper electrode. A gap formed between the vibrating film and the fixed film opposed to each other forms an air gap. The restraining portion provides partial coupling between the semiconductor substrate and the vibrating film, and the vibrating film has a multilayer structure in which the lower electrode and a compressive stress inducing insulating film are laminated. The insulating film is located within the perimeter of the lower electrode.
    Type: Application
    Filed: May 17, 2011
    Publication date: September 8, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: TOHRU YAMAOKA, YUICHI MIYOSHI, YUSUKE TAKEUCHI
  • Publication number: 20100254561
    Abstract: Provided is a microphone device, i.e., an acoustic sensor, with high reliability for reducing noise caused by light. A microphone device includes: a condenser including a first electrode, and a second electrode opposite to the first electrode, the first electrode and the second electrode are provided on a semiconductor substrate; an amplifier which is electrically connected to the condenser. Each of the first electrode and the second electrode has the same conductivity type as the semiconductor substrate.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 7, 2010
    Applicant: Panasonic Corporation
    Inventors: Norio KIMURA, Hiroshi Ogura, Yusuke Takeuchi
  • Publication number: 20100189289
    Abstract: An object of the invention is to design microminiaturization and higher sensitivity of a capacitor microphone chip formed by micromachining a silicon substrate and a wafer is diced so that a silicon substrate of a microphone chip is shaped almost like a hexagon, preferably a regular hexagon, and a back air chamber is shaped like a circle or a regular hexagon.
    Type: Application
    Filed: June 27, 2007
    Publication date: July 29, 2010
    Inventor: Yusuke Takeuchi
  • Publication number: 20100162821
    Abstract: A MEMS device includes: a substrate having a through hole; a first film provided on a top surface of the substrate with a bottom surface of the first film exposed in the through hole; a second film provided over the first film with an air gap interposed therebetween, and having a hole grouping including holes each in communication with the air gap; and a supporting layer interposed between the first and second films and having the air gap formed therein. Outermost holes of the hole grouping are located at regular intervals along a shape of an opening of the through hole at an upper open end.
    Type: Application
    Filed: November 18, 2009
    Publication date: July 1, 2010
    Inventor: Yusuke TAKEUCHI
  • Publication number: 20100077863
    Abstract: A diaphragm structure for a MEMS device includes a through-hole formed so as to penetrate from an upper surface to a bottom surface of a substrate; and a vibrating electrode film formed on the upper surface of the substrate so as to cover the through-hole. An opening shape of the through-hole in the upper surface of the substrate is substantially hexagonal.
    Type: Application
    Filed: December 3, 2009
    Publication date: April 1, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichi MIYOSHI, Yusuke Takeuchi, Tohru Yamaoka, Hiroshi Ogura
  • Publication number: 20100059836
    Abstract: A MEMS device, including: a substrate having a first principal plane and a second principal plane opposite to the first principal plane; a through hole formed in the substrate; and a vibrating film formed over the first principal plane so as to cover the through hole. The first principal plane and the second principal plane are both a (110) crystal face; and the through hole has a substantially rhombic shape on the second principal plane.
    Type: Application
    Filed: May 6, 2009
    Publication date: March 11, 2010
    Inventors: Yuichi Miyoshi, Tohru Yamaoka, Hidenori Notake, Yusuke Takeuchi
  • Publication number: 20090129612
    Abstract: A new electretization technology for a silicon microphone capable of reasonably electretizing a dielectric film of a condenser microphone formed by micromachining a silicon substrate and also capable of taking measures against variations in the microphone sensitivity caused by manufacturing variations and characteristic variations in parts is provided. A silicon microphone chip is completed and is implemented on an printed-circuit board and in this state, electretization processing is executed separately for a dielectric film in one silicon microphone chip by executing corona discharge using one needle electrode 51. More than one electretization is executed and the second or later electretization quantity is determined adaptively based on the actual measurement result of the microphone sensitivity, whereby electretization of the dielectric film is executed precisely and efficiently.
    Type: Application
    Filed: June 5, 2006
    Publication date: May 21, 2009
    Inventors: Yusuke Takeuchi, Hiroshi Ogura, Katuhiro Makihata
  • Patent number: 7508117
    Abstract: To implement a piezoelectric actuator which can actuate a large object, such as an imaging element, in a predetermined direction at high power without involvement of rotational displacement; which can ensure a large amount of actuation; which is suitable for miniaturization and weight reduction; and which is advantageous in terms of mechanical durability and manufacturing cost. A piezoelectric actuator having a well-balanced mechanical structure is obtained by means of stacking a plurality of cross units, in each of which a pair of bimorph piezoelectric elements (21a and 21b, 21c and 21d) are crossed in the form of the letter X, into two layers (an even number of layers), and fixing the thus-stacked cross units. An imaging element 11 is stably supported by means of two movable ends (C-1, C-2) provided at the extremity of the piezoelectric actuator.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: March 24, 2009
    Assignee: Panasonic Corporation
    Inventor: Yusuke Takeuchi
  • Publication number: 20070284968
    Abstract: To implement a piezoelectric actuator which can actuate a large object, such as an imaging element, in a predetermined direction at high power without involvement of rotational displacement; which can ensure a large amount of actuation; which is suitable for miniaturization and weight reduction; and which is advantageous in terms of mechanical durability and manufacturing cost. A piezoelectric actuator having a well-balanced mechanical structure is obtained by means of stacking a plurality of cross units, in each of which a pair of bimorph piezoelectric elements (21a and 21b, 21c and 21d) are crossed in the form of the letter X, into two layers (an even number of layers), and fixing the thus-stacked cross units. An imaging element 11 is stably supported by means of two movable ends (C-1, C-2) provided at the extremity of the piezoelectric actuator.
    Type: Application
    Filed: October 18, 2005
    Publication date: December 13, 2007
    Inventor: Yusuke Takeuchi
  • Publication number: 20070274544
    Abstract: While a dielectric film is set to have a ground potential, a fixed electrode is set to have a different potential from the ground potential. Thereafter, ions produced by corona discharge are allowed to pass through a plurality of acoustic holes formed in the fixed electrode and reach the dielectric film, thereby electretizing the dielectric film.
    Type: Application
    Filed: February 6, 2007
    Publication date: November 29, 2007
    Inventors: Yusuke Takeuchi, Hiroshi Ogura
  • Patent number: 7216269
    Abstract: A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 8, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Takashige Baba, Tatsuya Saito, Hiroki Yamashita, Yusuke Takeuchi, Satoru Isomura
  • Publication number: 20040218665
    Abstract: A signal transmit-receive device that reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group and for running a loopback test on a signal transmit-receive device for signal communication, and reduces installation costs and power consumption. The new loopback test circuit uses an error detecting circuit within the transmitting circuit IC, a test signal producing circuit within the receiving circuit IC, and a wiring for transmitting error information from the transmitting circuit to the receiving circuit. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern to detect errors. The test signal producing circuit produces a test signal pattern defined in advance by the first communication device, and can invert any bits of the test signal pattern, based on error information.
    Type: Application
    Filed: December 5, 2002
    Publication date: November 4, 2004
    Inventors: Takashige Baba, Tatsuya Saito, Hiroki Yamashita, Yusuke Takeuchi, Satoru Isomura
  • Patent number: 6476750
    Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Katsuhiro Furukawa
  • Publication number: 20020130369
    Abstract: The present invention provides a semiconductor integrated circuit device comprising a digital circuit and an analog circuit on a common substrate wherein a substrate effect constant of the analog circuit is at least less than a substrate effect constant of the digital circuit and wherein the analog circuit further comprises a P type polysilicon gate electrode for a nMOSFET and a N type polysilicon gate electrode for a pMOSFET.
    Type: Application
    Filed: August 10, 2001
    Publication date: September 19, 2002
    Inventors: Takayuki Iwasaki, Yusuke Takeuchi, Atsuo Watanabe
  • Patent number: 6445055
    Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor 11d in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 11a to 11d can increase the withstand voltage of a semiconductor integrated circuit.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: September 3, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
  • Publication number: 20020017686
    Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor lid in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 1a to 11d can increase the withstand voltage of a semiconductor integrated circuit.
    Type: Application
    Filed: August 9, 2001
    Publication date: February 14, 2002
    Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
  • Patent number: 6344809
    Abstract: In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Yasuo Shima
  • Patent number: D517534
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: March 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Ogura, Katsuhiro Makihata, Yusuke Takeuchi