Abstract: A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.

Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.

Abstract: A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases.

Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of planes that are independently operable, a plurality of first output terminals through which data read from the memory cell array are output, a second output terminal through which a ready/busy signal indicating a ready/busy state of the memory cell array is output, a control circuit configured to generate a first signal indicating a ready/busy state of each of the plurality of planes, and a signal converter configured to convert the first signal to a second signal indicating a ready/busy state of each of the plurality of planes, the second signal being output through the second output terminal.

Abstract: An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test pattern data into a storage area of the semiconductor integrated circuit.

Abstract: A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.

Abstract: An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test pattern data into a storage area of the semiconductor integrated circuit.

Abstract: A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part.

Abstract: A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.

Abstract: A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part.