Patents by Inventor Yusuke Tanuma

Yusuke Tanuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12148680
    Abstract: A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: November 19, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko Akiba, Yusuke Tanuma
  • Publication number: 20220165638
    Abstract: A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 26, 2022
    Inventors: Toshihiko AKIBA, Yusuke TANUMA
  • Patent number: 11049786
    Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Tsuchiya, Shuuichi Kariyazaki, Takashi Kikuchi, Michiaki Sugiyama, Yusuke Tanuma
  • Publication number: 20200135607
    Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventors: Keita TSUCHIYA, Shuuichi KARIYAZAKI, Takashi KIKUCHI, Michiaki SUGIYAMA, Yusuke TANUMA
  • Patent number: 10553558
    Abstract: A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Katsura, Yusuke Tanuma
  • Publication number: 20170053846
    Abstract: A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 23, 2017
    Inventors: Yosuke KATSURA, Yusuke TANUMA
  • Patent number: 8389339
    Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Tanuma, Toshikazu Ishikawa
  • Publication number: 20120083073
    Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.
    Type: Application
    Filed: September 16, 2011
    Publication date: April 5, 2012
    Inventors: Yusuke TANUMA, Toshikazu Ishikawa