Abstract: A semiconductor memory device includes a first conductive layer, a first and a second semiconductor layer opposed to the first conductive layer, a first and a second electric charge accumulating portion disposed between the first conductive layer and the first and the second semiconductor layer, and a first and a second bit line electrically connected to the first and the second semiconductor layer. A distance from a center position of the first conductive layer to the second semiconductor layer is smaller than a distance from the center position of the first conductive layer to the first semiconductor layer. When a read operation is executed on a first memory cell including the first electric charge accumulating portion and a second memory cell including the second electric charge accumulating portion, a voltage of the second bit line is larger than a voltage of the first bit line.

Abstract: A semiconductor memory device includes a first conductive layer, a first and a second semiconductor layer opposed to the first conductive layer, a first and a second electric charge accumulating portion disposed between the first conductive layer and the first and the second semiconductor layer, and a first and a second bit line electrically connected to the first and the second semiconductor layer. A distance from a center position of the first conductive layer to the second semiconductor layer is smaller than a distance from the center position of the first conductive layer to the first semiconductor layer. When a read operation is executed on a first memory cell including the first electric charge accumulating portion and a second memory cell including the second electric charge accumulating portion, a voltage of the second bit line is larger than a voltage of the first bit line.

Abstract: At a time of writing first data to a first memory cell, second data which is written later to an adjacent second memory cell is referred to, and when a value of the second data corresponds to a first threshold level, a verify voltage is set to a first verify voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, the verify voltage is set to a second verify voltage smaller than the first verify voltage.

Abstract: At a time of writing first data to a first memory cell, second data which is written later to an adjacent second memory cell is referred to, and when a value of the second data corresponds to a first threshold level, a verify voltage is set to a first verify voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, the verify voltage is set to a second verify voltage smaller than the first verify voltage.

Abstract: According to one embodiment, selection gates include an extract portion, a first portion, and a second portion. A predetermined potential is transmitted from the extract portion to the first portion. The predetermined potential is transmitted from the extract portion to the second portion with a delayed time to the first portion. A threshold voltage of a first selection transistor is different from a threshold voltage of a second selection transistor. The first selection transistor includes a semiconductor body disposed in the first portion as a channel. The second selection transistor includes the semiconductor body disposed in the second portion as a channel.

Abstract: A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.

Abstract: A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members. The control circuit classifies the memory cells into a first group and a second group. The control circuit performs writing, reading, and erasing of n-value data (n being an integer of two or more) on the memory cell of the first group. The control circuit performs writing, reading, and erasing of m-value data (m being an integer larger than n) on the memory cell of the second group.

Abstract: According to one embodiment, selection gates include an extract portion, a first portion, and a second portion. A predetermined potential is transmitted from the extract portion to the first portion. The predetermined potential is transmitted from the extract portion to the second portion with a delayed time to the first portion. A threshold voltage of a first selection transistor is different from a threshold voltage of a second selection transistor. The first selection transistor includes a semiconductor body disposed in the first portion as a channel. The second selection transistor includes the semiconductor body disposed in the second portion as a channel.

Abstract: A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members. The control circuit classifies the memory cells into a first group and a second group. The control circuit performs writing, reading, and erasing of n-value data (n being an integer of two or more) on the memory cell of the first group. The control circuit performs writing, reading, and erasing of m-value data (m being an integer larger than n) on the memory cell of the second group.

Abstract: A semiconductor device according to an embodiment includes first and second memory cells, a first word line, and first and second bit lines. The first memory cell has a first gate electrode and a first channel. The second memory cell has a second gate electrode and a second channel. The first word line connected with each of the first and second gate electrodes. The first and second bit lines electrically connected with the first and second channels, respectively. The semiconductor device erases data of each of the first and second memory cells, and then shifts respective threshold voltages of the first and second memory cells while making a first voltage between the first gate electrode and the first channel, and a second voltage between the second gate electrode and the second channel. The first voltage is different from the second voltage.

Abstract: A semiconductor device according to an embodiment includes first and second memory cells, a first word line, and first and second bit lines. The first memory cell has a first gate electrode and a first channel. The second memory cell has a second gate electrode and a second channel. The first word line connected with each of the first and second gate electrodes. The first and second bit lines electrically connected with the first and second channels, respectively. The semiconductor device erases data of each of the first and second memory cells, and then shifts respective threshold voltages of the first and second memory cells while making a first voltage between the first gate electrode and the first channel, and a second voltage between the second gate electrode and the second channel. The first voltage is different from the second voltage.

Abstract: A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n?3)th (n being a natural number) bit line and the memory cell connected to the (4n?2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n?1)th bit line and the memory cell connected to the 4nth bit line.

Abstract: A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line.

Abstract: A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line.

Abstract: The present invention provides a new means for improving the foam quality, especially foam stability, of beer-taste beverages. Specifically, the amount of mugi-derived extract components in beer-taste beverages is adjusted to lie from 0.1 to 2 wt % inclusive.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n?3)th (n being a natural number) bit line and the memory cell connected to the (4n?2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n?1)th bit line and the memory cell connected to the 4nth bit line.

Abstract: The present invention provides a new means for improving the foam quality, especially foam stability, of unfermented, non-alcoholic beer-taste beverages. Specifically, the amount of mugi-derived extract components in unfermented, non-alcoholic beer-taste beverages is adjusted to lie from 0.1 to 2 wt % inclusive.

Abstract: The present invention provides a new means for improving the foam quality, especially foam stability, of beer-taste beverages. Specifically, the amount of mugi-derived extract components in beer-taste beverages is adjusted to lie from 0.1 to 2 wt % inclusive.

Abstract: A novel technique is provided for drying a yeast for brewing and a method of producing alcoholic beverages by using the yeast. It is intended to provide a method of producing a dry yeast which has the optimum fermentability when directly used in fermentation and gives an appropriate flavor without needing prepropagation, and a method of producing alcoholic beverages by using the yeast. A method comprising incorporating a stabilizer such as trehalose into a yeast which has been recovered from the fermentation step, and, if desired, further incorporating glycerol into the yeast to thereby lower the water activity in the cells, and then dehydrating/drying the yeast while sustaining a high viable cell ratio and favorable fermentability; and alcoholic beverages produced by using the yeast.