Abstract: An apparatus and system for vehicle application management. The apparatus includes: at least one storage storing instructions; and at least one processor configured to execute the instructions to perform operations including: obtaining information identifying a first plurality of vehicle applications selected by a user of the vehicle and determining, for the user, a user-specific application matrix comprising first weight values. Each one of the first weight values is for a respective one of the first plurality of vehicle applications, and each one of the first weight values is determined based on at least a frequency of use, by the user, of the respective one of the first plurality of vehicle applications. The operations also include controlling, using the determined user-specific application matrix, downloading and installation, at the vehicle, of at least one of the first plurality of vehicle applications that is not currently installed in the vehicle.

Abstract: In order to perform a discrimination calculation using a small-capacity storage unit, a discrimination calculation apparatus comprises a feature calculation unit configured to sequentially calculate a feature of discrimination target data for each hierarchical layer, a discrimination calculation unit configured to sequentially perform a partial discrimination calculation on the discrimination target data using the feature sequentially calculated by the feature calculation unit and store a result of the partial discrimination calculation in a discrimination result storage unit, and a control unit configured to control the discrimination calculation unit to perform a next partial discrimination calculation using the feature sequentially calculated by the feature calculation unit and the result of the partial discrimination calculation stored in the discrimination result storage unit and to store a result of the next partial discrimination calculation in the discrimination result storage unit.

Abstract: To allow arithmetic processing using a plurality of processing nodes to be executed with a smaller memory size, an arithmetic processing apparatus for executing processing using a hierarchical type network formed by the plurality of processing nodes, comprises: a storage unit configured to store a parameter used by each of the plurality of processing nodes for arithmetic processing and a calculation result of the arithmetic processing in each of the plurality of processing nodes; and a buffer control unit configured to switch, based on a configuration of the hierarchical type network, a buffer system of the parameter and the calculation result in the storage unit in at least one layer of the hierarchical type network.

Abstract: A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.

Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.

Abstract: In order to perform a discrimination calculation using a small-capacity storage unit, a discrimination calculation apparatus comprises a feature calculation unit configured to sequentially calculate a feature of discrimination target data for each hierarchical layer, a discrimination calculation unit configured to sequentially perform a partial discrimination calculation on the discrimination target data using the feature sequentially calculated by the feature calculation unit and store a result of the partial discrimination calculation in a discrimination result storage unit, and a control unit configured to control the discrimination calculation unit to perform a next partial discrimination calculation using the feature sequentially calculated by the feature calculation unit and the result of the partial discrimination calculation stored in the discrimination result storage unit and to store a result of the next partial discrimination calculation in the discrimination result storage unit.

Abstract: A method of configuring a System on Chip to execute a CNN process comprising CNN layers, the method comprising, for each schedule: determining memory access amount information describing how many memory accesses are required; expressing the memory access amount information as relationships describing reusability of data; combining the relationships with a cost of writing and reading from external memory, to form memory access information; determining a memory allocation for on-chip memory of the SoC for the input FMs and the output FMs; and determining, dependent upon the memory access information and the memory allocation for each schedule; a schedule which minimises the memory access information of external memory access for the CNN layer of the CNN process; and a memory allocation associated with the determined schedule.

Abstract: A method of configuring a System on Chip to execute a CNN process comprising CNN layers, the method comprising, for each schedule: determining memory access amount information describing how many memory accesses are required; expressing the memory access amount information as relationships describing reusability of data; combining the relationships with a cost of writing and reading from external memory, to form memory access information; determining a memory allocation for on-chip memory of the SoC for the input FMs and the output FMs; and determining, dependent upon the memory access information and the memory allocation for each schedule; a schedule which minimises the memory access information of external memory access for the CNN layer of the CNN process; and a memory allocation associated with the determined schedule.

Abstract: To allow arithmetic processing using a plurality of processing nodes to be executed with a smaller memory size, an arithmetic processing apparatus for executing processing using a hierarchical type network formed by the plurality of processing nodes, comprises: a storage unit configured to store a parameter used by each of the plurality of processing nodes for arithmetic processing and a calculation result of the arithmetic processing in each of the plurality of processing nodes; and a buffer control unit configured to switch, based on a configuration of the hierarchical type network, a buffer system of the parameter and the calculation result in the storage unit in at least one layer of the hierarchical type network.

Abstract: A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.

Abstract: A method of determining a metric of a System-on-Chip (SoC), the method comprising: receiving a model dependency graph representing the SoC, the model dependency graph having a plurality of nodes representing components of the SoC and their models, and a plurality of directed edges between the nodes representing variables passed between the nodes of the model dependency graph; modifying the model dependency graph by clustering a plurality of strongly connected nodes in the model dependency graph into a single clustered node to form a clustered model dependency graph; determining an execution schedule according to a direction of an edge in the clustered model dependency graph; and executing models in the clustered model dependency graph according to the execution schedule to determine metrics of the SoC.

Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.

Abstract: An edge graph in which a pixel of an image is set as a node and an edge is set between nodes is generated. The dissimilarity or similarity between nodes at the two ends of the edge is used as the feature amount of the edge, and the edge is classified into one of a plurality of classes based on the feature amount. The edge of interest is selected in ascending class order of the feature amount, and it is determined whether to merge determination target regions to which the nodes at the two ends of the edge of interest belong. Determination target regions determined to be able to be merged are merged, and a feature amount in the merged region is updated.

Abstract: According to the present invention, in changing the circuit configuration of a reconfigurable device, a circuit configuration change period is shortened while avoiding a dependency on processing contents without increasing the size of a circuit due to addition of a mechanism. Considering an execution order relation between a plurality of data flows, a setting change count necessary for changing the circuit configuration in changing processing is decreased within a constraint range, thereby shortening the circuit configuration change period.

Abstract: A method of determining a metric of an SoC, the method comprising: receiving a model dependency graph representing the SoC, the model dependency graph having a plurality of nodes representing components of the SoC and their models, and a plurality of directed edges between the nodes representing variables passed between the nodes of the model dependency graph; modifying the model dependency graph by clustering a plurality of strongly connected nodes in the model dependency graph into a single clustered node to form a clustered model dependency graph; determining an execution schedule according to a direction of an edge in the clustered model dependency graph; and executing models in the clustered model dependency graph according to the execution schedule to determine metrics of the SoC.

Abstract: An edge graph in which a pixel of an image is set as a node and an edge is set between nodes is generated. The dissimilarity or similarity between nodes at the two ends of the edge is used as the feature amount of the edge, and the edge is classified into one of a plurality of classes based on the feature amount. The edge of interest is selected in ascending class order of the feature amount, and it is determined whether to merge determination target regions to which the nodes at the two ends of the edge of interest belong. Determination target regions determined to be able to be merged are merged, and a feature amount in the merged region is updated.

Abstract: According to the present invention, in changing the circuit configuration of a reconfigurable device, a circuit configuration change period is shortened while avoiding a dependency on processing contents without increasing the size of a circuit due to addition of a mechanism. Considering an execution order relation between a plurality of data flows, a setting change count necessary for changing the circuit configuration in changing processing is decreased within a constraint range, thereby shortening the circuit configuration change period.