Patents by Inventor Yusuke YAHATA

Yusuke YAHATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105520
    Abstract: A planar antenna includes a dielectric substrate, a feed line on a first surface of the dielectric substrate that has a first and second lateral sides, three rectangular-shaped radiation elements arrayed on the first surface and provided at the first and second lateral sides to alternately protrude, and an electromagnetic band gap structure having an arrangement region on the first surface. The first surface includes a first adjacent region adjacent to the first lateral side and a second adjacent region adjacent to the second lateral side. The arrangement region includes a first arrangement region in the first adjacent region and a second arrangement region in the second adjacent region. Part of the first arrangement region is closer to the feed line with respect to a first imaginary line, and part of the second arrangement region is closer to the feed line with respect to a second imaginary line.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 27, 2025
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke YAHATA, Ichiro KUWAYAMA, Suguru YAMAGISHI, Yutaro MIKI
  • Publication number: 20230417905
    Abstract: A radar antenna of the disclosure is a radar antenna unit including a receiving antenna configured to receive a reflected wave of a radar wave. The receiving antenna includes a plurality of receiving antenna elements arranged at an interval so as to form a row along a first direction. The plurality of receiving antenna elements include a first end antenna element positioned at a first end of the row, a second end antenna element positioned at a second end of the row, and a plurality of intermediate antenna elements positioned between the first end antenna element and the second end antenna element. Of a plurality of the intervals between the plurality of receiving antenna elements, at least one interval differs from other interval. The plurality of receiving antenna elements are disposed such that PL+PR?PAVG×2 holds. PAVG is from 0.8 ?0 to 1.2 ?0. PL is a first end interval.
    Type: Application
    Filed: November 18, 2021
    Publication date: December 28, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaro MIKI, Suguru YAMAGISHI, Takanori FUKUNAGA, Ichiro KUWAYAMA, Hideaki SHIRANAGA, Nobuo HIGASHIDA, Eiji MOCHIDA, Shohei OGAWA, Yusuke YAHATA
  • Publication number: 20230318533
    Abstract: An amplifier module includes a Doherty amplifier circuit, and the Doherty amplifier circuit includes a first transistor chip constituting a carrier amplifier, a first output signal line configured to transmit a first amplified signal outputted from the carrier amplifier, a second transistor chip constituting a peak amplifier, and a second output signal line configured to transmit a synthetic signal of the first amplified signal and a second amplified signal outputted from the peak amplifier. A direction from a drain terminal of the second transistor chip to a connection, of the first conductor of the first output signal line, with the first bonding wire is the same direction as a direction from the drain terminal of the second transistor chip to a connection, of the second conductor of the second output signal line, with the second bonding wire.
    Type: Application
    Filed: May 24, 2021
    Publication date: October 5, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Yusuke YAHATA
  • Publication number: 20230135728
    Abstract: A high frequency circuit module mounted on a first board that is a printed circuit board, includes: a second board; a high frequency circuit disposed on a first surface of the second board; a high frequency signal line disposed on the first surface of the second board, and extending from the high frequency circuit; and a matching member disposed on the first surface so as to cover at least a part of the high frequency signal line, and configured to adjust an impedance in the high frequency signal line. The matching member includes: a reference potential conductor separated from the high frequency signal line in a direction from a second surface, of the second board, opposite to the first surface, toward the first surface, the reference potential conductor being set at a reference potential; and a dielectric disposed between the reference potential conductor and the high frequency signal line.
    Type: Application
    Filed: April 30, 2021
    Publication date: May 4, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Mikoto NAKAMURA, Yusuke YAHATA