Abstract: A bias circuit for applying bias current to a low quiescent current amplifier includes first and second transistors and a transistor pair circuit. The first transistor is connected to a supply bias voltage source and an auxiliary bias voltage source, and is controlled by a bias voltage output from the auxiliary bias voltage source, the first transistor acting as a current source. The second transistor is connected to the supply bias voltage source and an output of the first transistor, and is controlled by the output of the first transistor to selectively buffer supply bias current from the supply bias voltage source provided to the low quiescent current amplifier via a bias resistor. The transistor pair circuit includes third and fourth transistors connected in series, one of the third and fourth transistors is also connected in parallel with a dividing resistor, the transistor pair circuit acting as a voltage source.

Abstract: A bias circuit for applying bias current to a low quiescent current amplifier includes first and second transistors and a transistor pair circuit. The first transistor is connected to a supply bias voltage source and an auxiliary bias voltage source, and is controlled by a bias voltage output from the auxiliary bias voltage source, the first transistor acting as a current source. The second transistor is connected to the supply bias voltage source and an output of the first transistor, and is controlled by the output of the first transistor to selectively buffer supply bias current from the supply bias voltage source provided to the low quiescent current amplifier via a bias resistor. The transistor pair circuit includes third and fourth transistors connected in series, one of the third and fourth transistors is also connected in parallel with a dividing resistor, the transistor pair circuit acting as a voltage source.

Abstract: A system comprises a power amplifier configured to amplify an input signal, a splitter configured to split the amplified input signal into a plurality of output signals, a plurality of filters configured to filter the plurality of output signals, respectively, to produce a plurality of filtered output signals, and a combiner configured to combine the filtered output signals to produce a combined output signal.

Abstract: A system comprises a power amplifier configured to amplify an input signal, a splitter configured to split the amplified input signal into a plurality of output signals, a plurality of filters configured to filter the plurality of output signals, respectively, to produce a plurality of filtered output signals, and a combiner configured to combine the filtered output signals to produce a combined output signal.

Abstract: A monolithic microwave integrated circuit (MMIC) includes a transistor, coupled line and multiple air bridges. The coupled line is configured to output a coupled signal from the transistor, the coupled line running parallel to a drain of the transistor. The air bridges connect the drain of the transistor with a bond pad for outputting a transistor output signal, the bridges being arranged parallel to one another and extending over the coupled line. The air bridges and the coupled line effectively provide coupling of the transistor output signal to a load.

Abstract: A monolithic microwave integrated circuit (MMIC) includes a transistor, coupled line and multiple air bridges. The coupled line is configured to output a coupled signal from the transistor, the coupled line running parallel to a drain of the transistor. The air bridges connect the drain of the transistor with a bond pad for outputting a transistor output signal, the bridges being arranged parallel to one another and extending over the coupled line. The air bridges and the coupled line effectively provide coupling of the transistor output signal to a load.

Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.

Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.

Abstract: An RF switching circuit that incorporates a film bulk acoustic resonator (FBAR) device and one or more capacitors that are used to vary the capacitance of the FBAR device to change the frequency range that is blocked by the FBAR device. When the RF switching circuit is in a first switching state, a first set of RF signals in a first frequency range is blocked by the RF switching circuit while RF signals of other frequencies are passed by the RF switching circuit. When the RF switching circuit is in a second switching state, a second set of RF signals in a second frequency range is blocked by the RF switching circuit while RF signals of other frequencies are passed by the RF switching circuit.

Abstract: A low noise amplifier and method for amplifying an input signal uses a high impedance electrical element having both inductance and capacitance connected between an output transistor and a bias circuit to provide noise isolation between the bias circuit and the output transistor. The noise isolation provided by the high impedance electrical element reduces the amount of bias circuit noise introduced into the output signal. In an embodiment, the high impedance electrical element includes an inductor and a capacitor connected in parallel. In another embodiment, the high impedance electrical element includes a grounded transmission line.

Abstract: An amplifier having first and second enhancement-mode Field Effect Transistors (FETs) is disclosed. The input port receives an input signal that is to be amplified. The source of the first FET is connected to the input port such that the first FET provides an input impedance match for a signal source connected to the input port. The gate of the second FET is connected to the drain of the first FET such that the second FET amplifies the output signal from the drain of the first FET to provide an amplified input signal. The first and second FETs form a current mirror. An output circuit provides a predetermined output impedance at an output port for coupling the amplified input signal to a circuit that is external to the amplifier. In one embodiment of the invention, the output circuit includes a third FET connected as a source follower with the second FET.

Abstract: An amplifier having first and second enhancement-mode Field Effect Transistors (FETs) is disclosed. The input port receives an input signal that is to be amplified. The source of the first FET is connected to the input port such that the first FET provides an input impedance match for a signal source connected to the input port. The gate of the second FET is connected to the drain of the first FET such that the second FET amplifies the output signal from the drain of the first FET to provide an amplified input signal. The first and second FETs form a current mirror. An output circuit provides a predetermined output impedance at an output port for coupling the amplified input signal to a circuit that is external to the amplifier. In one embodiment of the invention, the output circuit includes a third FET connected as a source follower with the second FET.