Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

Abstract: A temperature-detecting device includes a frame, a temperature-detecting unit, a driving unit, a rotation-controlling unit, and a controller. The temperature-detecting unit includes a sensor, a sensor cap, and a sensor case. The rotation-controlling unit is configured to stop rotation of the sensor cap when the temperature-detecting unit reaches a target angle that is over 360 degrees froma reference position, with the sensor case being kept rotated by the driving unit such that the sensor is displaced froman opening and is covered by the sensor case. The controller is configured to correct a temperature detected while the sensor is exposed at the opening, with reference to a temperature detected while the sensor is covered by the sensor case.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

Abstract: According to one embodiment, an information processing device includes a processor configured to refer to address conversion data. The address conversion data has a plurality of logical addresses associated with a plurality of physical addresses of a storage device. The processor converts the plurality of logical addresses of an evaluation target in storage device into the corresponding plurality of physical addresses for the evaluation target by referring to the address conversion data. The processor then calculates an evaluation value indicating a parallel reading performance for the plurality of physical addresses of the evaluation target using a parameter specifying a number of areas of the storage device readable in parallel.

Abstract: According to one embodiment, an information processing device includes a processor configured to refer to address conversion data. The address conversion data has a plurality of logical addresses associated with a plurality of physical addresses of a storage device. The processor converts the plurality of logical addresses of an evaluation target in storage device into the corresponding plurality of physical addresses for the evaluation target by referring to the address conversion data. The processor then calculates an evaluation value indicating a parallel reading performance for the plurality of physical addresses of the evaluation target using a parameter specifying a number of areas of the storage device readable in parallel.