Patents by Inventor Yuta Nomura
Yuta Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094673Abstract: A developing device includes: a container that contains developer; a developer holder that rotates with the developer being held on a surface thereof to transport the developer to a developing region; and a cooling unit. An introduction port is provided at a position corresponding to the developing region, the introduction port allowing suction of a floating substance generated in the developing region in a transverse direction of the container. The cooling unit is connected to the introduction port to allow passage of gas containing the floating substance in a longitudinal direction of the container, and cools the container with the gas. An intake port is connected to an end of the cooling unit in the longitudinal direction, the intake port allowing introduction of gas.Type: ApplicationFiled: January 13, 2023Publication date: March 21, 2024Applicant: FUJIFILM Business Innovation Corp.Inventors: Shunsuke YAMASAKI, Koji YOSHITSUGU, Yuta SHIMATATE, Yasuhisa GONDA, Kazunari ISHII, Yuka NOMURA
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Patent number: 11769736Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.Type: GrantFiled: April 14, 2021Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Yuta Nomura
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Patent number: 11715704Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.Type: GrantFiled: April 14, 2021Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Yoh Matsuda, Yuta Nomura
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Publication number: 20220336373Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Applicant: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Yoh Matsuda, Yuta Nomura
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Publication number: 20220336372Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Applicant: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Yuta Nomura
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Publication number: 20200052790Abstract: The present invention discloses an upper device connected to an opposing device by a communication line which is a carrier signal transmission line. The upper device includes one or a plurality of transceivers that mutually convert a carrier signal and an electrical signal; a line concentrator that has a first port for an upper network, a second port for the transceiver, and a third port for management communication, and sets a communication path between the ports; and a control unit for management communication connected to the third port. When there is no response message from the opposing device within a predetermined period of time after the control unit inputs a management frame destined for the opposing device and including control information for the opposing device, to the third port, the control unit reinputs the management frame to the third port.Type: ApplicationFiled: March 22, 2017Publication date: February 13, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Yuta NOMURA
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Patent number: 7884587Abstract: A charging unit charges a capacitor that is configured to be charged and discharged to drive a load. A switching unit switches on and off between the capacitor and the charging unit. A delay control unit delays an output of a switching control signal for controlling the switching unit until an output voltage of the charging unit exceeds a voltage of the capacitor, and outputs a delayed switching control signal. An output unit receives the delayed switching control signal from the delay control unit, and outputs the delayed switching control signal to the switching unit so that the charging unit charges the capacitor.Type: GrantFiled: August 7, 2008Date of Patent: February 8, 2011Assignee: Ricoh Company, LimitedInventors: Masae Sugawara, Yuta Nomura
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Publication number: 20090045792Abstract: A charging unit charges a capacitor that is configured to be charged and discharged to drive a load. A switching unit switches on and off between the capacitor and the charging unit. A delay control unit delays an output of a switching control signal for controlling the switching unit until an output voltage of the charging unit exceeds a voltage of the capacitor, and outputs a delayed switching control signal. An output unit receives the delayed switching control signal from the delay control unit, and outputs the delayed switching control signal to the switching unit so that the charging unit charges the capacitor.Type: ApplicationFiled: August 7, 2008Publication date: February 19, 2009Inventors: Masae Sugawara, Yuta Nomura