Abstract: A functional unit is synchronized with an output system unit on the basis of a trigger signal input from outside with a synchronization period. The input system unit includes: a functional processing unit to perform, on the basis of the trigger signal, a functional process with a control period that is shorter than the synchronization period, and to generate processing results by repeatedly performing the functional process in one synchronization period; and a shared memory to collectively output the processing results of the functional processing unit to outside on the basis of the trigger signal.

Abstract: A functional unit is synchronized with an output system unit on the basis of a trigger signal input from outside with a synchronization period. The input system unit includes: a functional processing unit to perform, on the basis of the trigger signal, a functional process with a control period that is shorter than the synchronization period, and to generate processing results by repeatedly performing the functional process in one synchronization period; and a shared memory to collectively output the processing results of the functional processing unit to outside on the basis of the trigger signal.

Abstract: A functional unit is synchronized with an output system unit on the basis of a trigger signal input from outside with a synchronization period. The input system unit includes: a functional processing unit to perform, on the basis of the trigger signal, a functional process with a control period that is shorter than the synchronization period, and to generate processing results by repeatedly performing the functional process in one synchronization period; and a shared memory to collectively output the processing results of the functional processing unit to outside on the basis of the trigger signal.

Abstract: A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.

Abstract: A functional unit is synchronized with an output system unit on the basis of a trigger signal input from outside with a synchronization period. The input system unit includes: a functional processing unit to perform, on the basis of the trigger signal, a functional process with a control period that is shorter than the synchronization period, and to generate processing results by repeatedly performing the functional process in one synchronization period; and a shared memory to collectively output the processing results of the functional processing unit to outside on the basis of the trigger signal.

Abstract: A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.