Patents by Inventor Yuta Tsubouchi

Yuta Tsubouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230328881
    Abstract: First and second conductors extend on and along a first surface of a substrate. The first conductor includes first and second parts extending in first and second directions and a third part connected to the first and second parts. The second conductor includes fourth and fifth parts extending in the first and second directions and a sixth part connected to the fourth and fifth parts. A first insulator partly covers the first surface, covers the first to fifth parts, and is partly opened in a first region extending along the sixth part above the sixth part in a third direction.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Yuta TSUBOUCHI
  • Patent number: 11723146
    Abstract: First and second conductors extend on and along a first surface of a substrate. The first conductor includes first and second parts extending in first and second directions and a third part connected to the first and second parts. The second conductor includes fourth and fifth parts extending in the first and second directions and a sixth part connected to the fourth and fifth parts. A first insulator partly covers the first surface, covers the first to fifth parts, and is partly opened in a first region extending along the sixth part above the sixth part in a third direction.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: August 8, 2023
    Assignee: Kioxia Corporation
    Inventor: Yuta Tsubouchi
  • Publication number: 20230090795
    Abstract: According to one embodiment, a semiconductor device includes receiving terminals on a surface of a substrate to receive first signals and transmitting terminals on the surface of the substrate to transmit second signals. The transmitting terminals are symmetrically positioned on the surface of the substrate with respect to the receiving terminals at a substantially 90 degree rotation about a rotation center position. The ordering of the transmitting terminals along the surface of the substrate from the rotation center position matches the ordering of the receiving terminals along the surface of the substrate from the rotation center position.
    Type: Application
    Filed: March 3, 2022
    Publication date: March 23, 2023
    Inventor: Yuta TSUBOUCHI
  • Publication number: 20230089773
    Abstract: First and second conductors extend on and along a first surface of a substrate. The first conductor includes first and second parts extending in first and second directions and a third part connected to the first and second parts. The second conductor includes fourth and fifth parts extending in the first and second directions and a sixth part connected to the fourth and fifth parts. A first insulator partly covers the first surface, covers the first to fifth parts, and is partly opened in a first region extending along the sixth part above the sixth part in a third direction.
    Type: Application
    Filed: December 15, 2021
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventor: Yuta Tsubouchi
  • Publication number: 20220408555
    Abstract: A printed board includes a first and second insulator extending in a first direction; a third insulator extending in a second direction and including a first and second portion located above and below the first insulator respectively in a third direction; a fourth insulator extending in the second direction, and including a third and fourth portion located below and above the first insulator respectively in the third direction; and a first and second conductor extending in the first direction, and arranged along the second direction with a first pitch therebetween. The first pitch is an n multiple of a first distance that is based on an interval between the first and second portion or the third and fourth portion. The n is an integer equal to or greater than 1.
    Type: Application
    Filed: March 15, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Yuta TSUBOUCHI
  • Patent number: 10623055
    Abstract: According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Daisuke Miyashita, Junji Wadatsumi, Jun Deguchi
  • Patent number: 10553284
    Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
  • Publication number: 20190089407
    Abstract: According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 21, 2019
    Inventors: Yuta Tsubouchi, Daisuke Miyashita, Junji Wadatsumi, Jun Deguchi
  • Patent number: 10236844
    Abstract: According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Junji Wadatsumi
  • Publication number: 20190074063
    Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 7, 2019
    Inventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
  • Publication number: 20180183395
    Abstract: According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.
    Type: Application
    Filed: September 8, 2017
    Publication date: June 28, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Junji Wadatsumi
  • Patent number: 8461900
    Abstract: An example frequency converting circuit generates a multiplied signal obtained by multiplying a local signal by an amplified signal generated by an amplifying portion. The frequency converting circuit includes a converter which converts the amplified signal into a current signal and a switching circuit which multiplies the current signal by the local signal and generates the multiplied signal. An impedance element supplies a first direct current from the amplifier and a second direct current from the switching circuit to the converter.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: June 11, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuta Tsubouchi, Toshiya Mitomo, Tong Wang
  • Publication number: 20120001667
    Abstract: A frequency converting apparatus according to one embodiment is a frequency converting circuit which generates a multiplied signal obtained by multiplying a local signal by an amplified signal generated by an amplifying portion comprising a first transistor having a drain terminal connected to a first power source potential, the frequency converting circuit comprising: a converter which comprises a second transistor of which gate terminal is connected to the amplifying portion and which converts the amplified signal inputted to the gate terminal into a current signal; a switching circuit which comprises two third-transistors of which a source terminal is connected each other and which multiplies the current signal by the local signal and generates the multiplied signal; and an impedance element which comprises a first terminal connected to a source terminal of the first transistor, a second terminal connected to a drain terminal of the second transistor and a third terminal connected to the source terminal of
    Type: Application
    Filed: July 5, 2011
    Publication date: January 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuta Tsubouchi, Toshiya Mitomo, Tong Wang