Abstract: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.

Abstract: A flow control device includes an analysis unit identifying a flow of a received packet, a plurality of queues temporarily storing packets sorted according to each flow, an allocation information storage unit storing allocation information regarding a queue allocated for each flow, a sorting unit deciding a queue to be a storage destination of the received packet and sorts the packet based on a result identified by the analysis unit and the allocation information, a saved packet holding unit saving a packet belonging to a flow determined to have no allocation information regarding the queue to be allocated by the sorting unit, and a transmission unit transmitting the packet temporarily stored in the plurality of queues and the packet saved in the saved packet holding unit to a processing unit that processes a packet.

Abstract: A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.

Abstract: A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.