Patents by Inventor Yutaka Amemiya

Yutaka Amemiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7946565
    Abstract: Imaging-system bookbinding apparatus avoids cutting any folded sheets mixed into booklets it trims. Furnished with: an imaging unit; a sheet-folding unit that folds imaging-unit sheets; a stacking unit that stacks sheets from the sheet-folding or image-forming units; a cover-sheet binding unit that encases stacking-unit sheet bundles with, and binds them into, cover sheets; a trimming unit that trims true the bundle fore-edge; and a fold-position computing unit that determines where a sheet is pleated by the sheet-folding unit. The sheet-folding unit has a sheet conveyance path along which folded sheets are transported elsewhere than the stacking unit, while the fold-position computing unit in a first control mode transports to the stacking unit sheets folded over by the sheet-folding unit, and in a second control mode transports them from the sheet conveyance path elsewhere than the stacking unit.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 24, 2011
    Assignee: Nisca Corporation
    Inventors: Kazuyuki Kubota, Kazuhide Sano, Tadahito Takano, Shinya Sasamoto, Yutaka Amemiya, Isao Kondo, Kenichi Yoshimura
  • Publication number: 20080237962
    Abstract: Imaging-system bookbinding apparatus avoids cutting any folded sheets mixed into booklets it trims. Furnished with: an imaging unit; a sheet-folding unit that folds imaging-unit sheets; a stacking unit that stacks sheets from the sheet-folding or image-forming units; a cover-sheet binding unit that encases stacking-unit sheet bundles with, and binds them into, cover sheets; a trimming unit that trims true the bundle fore-edge; and a fold-position computing unit that determines where a sheet is pleated by the sheet-folding unit. The sheet-folding unit has a sheet conveyance path along which folded sheets are transported elsewhere than the stacking unit, while the fold-position computing unit in a first control mode transports to the stacking unit sheets folded over by the sheet-folding unit, and in a second control mode transports them from the sheet conveyance path elsewhere than the stacking unit.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: NISCA CORPORATION
    Inventors: Kazuyuki Kubota, Kazuhide Sano, Tadahito Takano, Shinya Sasamoto, Yutaka Amemiya, Isao Kondo, Kenichi Yoshimura
  • Patent number: 5385624
    Abstract: A substrates treating apparatus comprising a chamber provided with a section at which a semiconductor wafer is treated and with another section at which plasma is generated. A supplier for supplying mixed gas (O.sub.2 +CF.sub.4) into the plasma generating section in the chamber, high frequency electrodes for changing the gas into plasma, an ion trap for trapping ions in the plasma to send neutral radicals into the wafer treating section, and an exhaust mechanism for exhausting the wafer treating section.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: January 31, 1995
    Assignee: Tokyo Electron Limited
    Inventors: Yutaka Amemiya, Akihito Toda
  • Patent number: 4812201
    Abstract: A method and an apparatus, both for ashing unnecessary layers such as a photoresist layer, formed on a semiconductor wafer, by applying ozone to the layer, are disclosed. An ashing gas containing oxygen atom radical, or containing oxygen gas and an ashing-promoting gas, is applied to the layer, thereby ashing the layer readily and efficiently. The surface temperature of the layer is set at a prescribed value, and the ashing gas is applied uniformly onto the entire surface of the layer, or onto a part thereof, thus ashing the whole layer, or a part thereof, uniformly at a high rate, and the end-point of the ashing process is detected, thereby to enhance the efficiency of the ashing process.
    Type: Grant
    Filed: July 15, 1987
    Date of Patent: March 14, 1989
    Assignee: Tokyo Electron Limited
    Inventors: Hiroyuki Sakai, Kazutoshi Yoshioka, Kimiharu Matsumura, Keisuke Shigaki, Yutaka Amemiya, Shunichi Iimuro, Haruhiko Yoshioka, Teruhiko Onoe