Abstract: In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelogram, and a second gate forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region and a drain region. In some embodiments, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient ? of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

Abstract: In a correlation process between image patterns seen by two stereo-viewing cameras, the process can be made faster by using only the information related to a coordinate in the direction having a parallax, concerning the position of a characteristic point in the image patterns. In addition, by introducing a process for verifying the positional information of the characteristic point obtained by a camera for verification, it is possible to suppress a decrease in the characteristic information contained in the image patterns and to improve the precision of the correlation process. As a result, it is possible to achieve a stereo image processing device which operates at high speed. Further, since the stereo image processing device can be realized by a comparatively simple circuit configuration, it is expected that the device can contribute to the commercialization of in-vehicle safety monitor devices and the like.

Abstract: Each pixel includes first and second photodiodes that are receiving-light detecting elements. The first photodiode applies a first potential according to an amount of light entering into the corresponding pixel. An internal node is electrically coupled with an internal node in another pixel via a resistance component. Hence, the second photodiode applies a second potential according to an average amount of light on the periphery to the corresponding internal node. A pixel signal generating circuit reads out a multiplied result of the first and second potentials as a pixel signal. The pixel signal has an intensity corresponding to the amount of light in the pixel in accordance with a receiving-light sensitivity characteristic (signal amplification factor) that is automatically adjusted based on an average amount of light in a region on the periphery of the pixel.

Abstract: A synapse configured of an A-MOS transistor has a learning function and can implement high integration similar to that of a DRAM because of its simplified circuit configuration and compact circuit size. With the presently cutting-edge technology (0.15 ?m CMOS), approximately 1G synapses can be integrated on one chip. Accordingly, it is possible to implement a neural network with approximately 30,000 neurons all coupled together on one chip. This corresponds to a network scale capable of associatively storing approximately 5,000 patterns.

Abstract: An inverter circuit which is a representative example of the logic circuit includes a p-channel A-MOS transistor and an n-channel transistor. The gain coefficient ? of the p-channel A-MOS transistor and n-channel transistor changes according to a voltage on a control gate. The control gate of the p-channel A-MOS transistor and n-channel MOS transistor is connected to an output node of the inverter circuit, and the normal MOS gate is connected to an input node of the inverter circuit. Thus, the ON resistance of the p-channel A-MOS transistor and n-channel transistor is automatically modulated to decrease as the source-drain voltage increases.

Abstract: A metal oxide semiconductor transistor includes a semiconductor substrate; a source area formed in a device area of the semiconductor substrate; a drain area formed in the device area; a gate layer formed on and across the device area between the source area and the drain area; a control gate layer; and a diffusion area formed in the device area between the gate area and the control gate area. The control gate layer has a first part including a first end of the control gate layer and a second part including a second end of the control gate layer. The first part is formed on the device area between the source area and the gate layer. The first end is disposed so that there is a gap between the first end and an edge of the device area.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: A metal oxide semiconductor transistor includes a semiconductor substrate; a source area located in a device area of the semiconductor substrate; a drain area located in the device area; a gate layer located on and across the device area between the source area and the drain area; a control gate layer; and a diffusion area located in the device area between the gate area and the control gate area. The control gate layer has a first part including a first end of the control gate layer and a second part including a second end of the control gate layer. The first part is located on the device area between the source area and the gate layer. There is a gap between the first end and an edge of the device area.

Abstract: A-MOS devices capable of continuously modulating a gain coefficient &bgr; in accordance with a voltage applied to a control gate provided in addition to a normal gate, are connected in an odd number of stages to configure a ring oscillator. An oscillation circuit can be implemented capable of modulating an oscillation frequency in accordance with the control gate's voltage in a wide range.

Abstract: In a correlation process between image patterns seen by two stereo-viewing cameras, the process can be made faster by using only the information related to a coordinate in the direction having a parallax, concerning the position of a characteristic point in the image patterns. In addition, by introducing a process for verifying the positional information of the characteristic point obtained by a camera for verification, it is possible to suppress a decrease in the characteristic information contained in the image patterns and to improve the precision of the correlation process. As a result, it is possible to achieve a stereo image processing device which operates at high speed. Further, since the stereo image processing device can be realized by a comparatively simple circuit configuration, it is expected that the device can contribute to the commercialization of in-vehicle safety monitor devices and the like.

Abstract: An inverter circuit which is a representative example of the logic circuit includes a p-channel A-MOS transistor and an n-channel transistor. The gain coefficient &bgr; of the p-channel A-MOS transistor and n-channel transistor changes according to a voltage on a control gate. The control gate of the p-channel A-MOS transistor and n-channel MOS transistor is connected to an output node of the inverter circuit, and the normal MOS gate is connected to an input node of the inverter circuit. Thus, the ON resistance of the p-channel A-MOS transistor and n-channel transistor is automatically modulated to decrease as the source-drain voltage increases.

Abstract: A-MOS devices capable of continuously modulating a gain coefficient &bgr; in accordance with a voltage applied to a control gate provided in addition to a normal gate, are connected in an odd number of stages to configure a ring oscillator. An oscillation circuit can be implemented capable of modulating an oscillation frequency in accordance with the control gate's voltage in a wide range.

Abstract: A synapse configured of an A-MOS transistor has a learning function and can implement high integration similar to that of a DRAM because of its simplified circuit configuration and compact circuit size. With the presently cutting-edge technology (0.15 &mgr;m CMOS), approximately 1G synapses can be integrated on one chip. Accordingly, it is possible to implement a neural network with approximately 30,000 neurons all coupled together on one chip. This corresponds to a network scale capable of associatively storing approximately 5,000 patterns.

Abstract: Each pixel includes first and second photodiodes that are receiving-light detecting elements. The first photodiode applies a first potential according to an amount of light entering into the corresponding pixel. An internal node is electrically coupled with an internal node in another pixel via a resistance component. Hence, the second photodiode applies a second potential according to an average amount of light on the periphery to the corresponding internal node. A pixel signal generating circuit reads out a multiplied result of the first and second potentials as a pixel signal. The pixel signal has an intensity corresponding to the amount of light in the pixel in accordance with a receiving-light sensitivity characteristic (signal amplification factor) that is automatically adjusted based on an average amount of light in a region on the periphery of the pixel.

Abstract: In a semiconductor device an electric field is controlled in direction or angle relative to a gate (101), or a channel to adjust a gain coefficient of a transistor. Preferably, there are provided a first gate (101) forming a channel region in a rectangle or a parallelogram, and a second gate (102) forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region (103) and a drain region (104). More preferably, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient &bgr; of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

Abstract: A semiconductor image pickup device includes a pixel array having pixels arranged in a matrix. Each pixel includes a photodiode that converts an optical signal into an electrical signal, and a transistor connected to a charge accumulation section of the photodiode. A buffer is additionally provided. This buffer controls the transistor of the pixels using a lower control power supply voltage than a power supply voltage of the pixel array.

Abstract: The associative memory-based computer includes at least one associative memory, a plurality of associative data memories capable of temporarily holding input or output data of the associative memory, and a value judgement device receiving part of the data held in the associative data memory. The associative memory is formed of a chaotic neural network. The associative data memories include a first associative data memory sending/receiving data directly to/from the associative memory, and a plurality of second associative data memories sending/receiving data to/from the associative memory via the first associative data memory.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: An image sensor which is capable of producing an output image superior in uniformity by correcting variations in the characteristics of solid state photosensing devices (pixels). Correction utilizes a correlation between a reset signal and sensitivity of the solid state photosensing devices, where the reset signal is produced by driving the solid state photosensing devices in a state in which no light is substantially incident. The solid state photosensing devices convert light into an electric output signal and a gain variable amplifier circuit amplifies the signal with a gain based on the reset signal. Saturation levels of the solid state photosensing devices, gains in the vicinity of the reset level, or both of them are corrected. This process removes the necessity to supply a reference signal of light in the image sensor.

Abstract: The semiconductor image pickup device comprises a pixel array having a plurality of pixels arranged in a matrix form. Each pixel comprises a photodiode that converts an optical signal into an electric signal, and a transistor connected to a charge accumulation section of the photodiode 3mn. A buffer is additionally provided. This buffer controls the transistor of the pixels using a lower control power supply voltage than a power supply voltage of the pixel array.