Abstract: The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Abstract: The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Abstract: A second trench is disposed in an inactive region, is in contact with an active region, and includes a second sidewall including a longitudinal portion and a lateral portion, and a second bottom. A second bottom diffusion layer of a second conductivity type is disposed at least in a part of the second bottom. A second sidewall diffusion layer of the second conductivity type is disposed at least on one of the longitudinal portion and the lateral portion. A gate electrode includes a gate buried portion buried in each of first trenches, and a gate line portion extending from the gate buried portion into the second trench. A second bottom diffusion layer is disposed at least in a portion of the second bottom on which the gate line portion is disposed in a plan view.

Abstract: An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

Abstract: In a silicon carbide semiconductor device, in a plan view, a plurality of source contact holes is intermittently provided in a second direction along a trench gate, and a source electrode is provided on an insulating film and is electrically connected to a source layer via the plurality of source contact holes. Intermittent recesses reflecting the shapes of the plurality of source contact holes are provided on a surface of the source electrode on a side opposite to the semiconductor substrate.

Abstract: An object of the present disclosure is to achieve low-resistance contact with pillar regions, reduce variations in withstand voltage, and reduce channel resistance and JFET resistance in a silicon carbide semiconductor device having an SJ structure and an insulated gate structure. An SJ-SiC-MOSFET includes an SJ region and an MOSFET region provided on the upper surface of the SJ region. The SJ region includes n-type first pillar regions and p-type second pillar regions that extend in a first direction parallel to a first main surface and that are alternately aligned in a second direction parallel to the first main surface and perpendicular to the first direction. The MOSFET region includes BPW regions extending in the second direction, connected to the second pillar regions, and aligned in the first direction at a second repetition interval that is shorter than a repetition interval of the second pillar regions.

Abstract: An object is to provide a technique capable of reducing a parasitic capacitance in a semiconductor device with high accuracy. A semiconductor device includes: a base region; a source region; a second trench passing through the base region to reach the drift layer; a second protective layer disposed in a bottom portion of the second trench; a source electrode, at least part of which is disposed in the second trench, to be electrically connected to a first protective layer, the base region, and the source region; and a source side connection layer of a second conductivity type constituting at least part of a lateral portion of the second trench and connected to the base region and the second protective layer.

Abstract: An object of the present invention is to provide a technique capable of reducing an energy loss during a switching operation. A first peripheral region includes a second bottom protection layer of a second conductivity type provided at a bottom of a second trench, and a second peripheral region includes a third bottom protection layer of the second conductivity type provided at a bottom of a third trench. The second bottom protection layer is electrically connected to a source electrode, the third bottom protection layer is electrically connected to a current sense electrode, or the second bottom protection layer and the third bottom protection layer are respectively electrically connected to the source electrode and the current sense electrode.

Abstract: The present invention relates to a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor and includes a first trench provided through first and second semiconductor regions in a thickness direction and reaches inside a semiconductor layer, a second trench provided through the second semiconductor region in the thickness direction and reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film, a Schottky barrier diode electrode embedded in the second trench, a first low-resistance layer having contact with a trench side wall of the first trench, and a second low-resistance layer having contact with a trench side wall of the second trench. The second low-resistance layer has an impurity concentration that is higher than the impurity concentration in the semiconductor layer and lower than the impurity concentration in the first low-resistance layer.

Abstract: A semiconductor device includes a plurality of trenches penetrating through a source region and a base region, and a mesa region as a region between two of the plurality of trenches. A gate electrode that faces the base region with a gate insulating film interposed between the gate electrode and the base region is formed in each trench. An electric field relieving layer is provided immediately below each trench. A super junction structure in which a first pillar layer and a second pillar layer are alternately arranged is formed between the base region and the drift layer. A width of the first pillar layer is equal to or less than a width of the electric field relieving layer.

Abstract: A drift layer is made of silicon carbide and has a first conductivity type. At least one trench has a first side surface facing a Schottky barrier diode region, and a second side surface extending in a transistor region and contacting a source region, a body region, and the drift layer. A first protective region is provided under the at least one trench, has a second conductivity type, and is higher in impurity concentration of the second conductivity type than the body region. A second protective region extends from the first protective region, reaches at least one of the first side surface and an end region of the second side surface continuous with the first side surface, has an uppermost portion shallower than a lowermost portion of the body region, and is higher in impurity concentration of the second conductivity type than the body region.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of forming gate trench, a step of forming Schottky trench, a step of forming a silicon oxide film in the gate trench and the Schottky trench, a step of forming a polycrystalline silicon film inside the silicon oxide film, a step of etching back the polycrystalline silicon film, a step of forming an interlayer insulating film on a gate electrode in the gate trench, a step of removing, by wet etching, the polycrystalline silicon film in the Schottky trench after opening a hole in the interlayer insulating film, a step of forming an ohmic electrode on a source region, a step of removing the silicon oxide film in the Schottky trench, and a step of forming a source electrode in the Schottky trench, which is in Schottky junction with a drift layer.

Abstract: A semiconductor device according to the present disclosure includes: a gate electrode provided in a gate trench and provided so as to oppose a source region via a gate insulating film; a first bottom protection region of a second conductivity type provided below the gate insulating film; a plurality of first connection regions of the second conductivity type provided at a first interval in an extension direction of the gate trench and electrically connecting the first bottom protection region and a body region; a Schottky electrode provided in a Schottky trench; a second bottom protection region of the second conductivity type provided below the Schottky electrode; and a plurality of second connection regions of the second conductivity type provided at a second interval smaller than the first interval in an extension direction of the Schottky trench and electrically connecting the second bottom protection region and the body region.

Abstract: A semiconductor device includes a trench-type switching element formed in an active region and a trench-type current sense element formed in a current sense region. Below a trench in which a gate electrode of the switching element is embedded, a trench in which a gate electrode of the current sense element is embedded, and a trench formed at the boundary portion between the active region and the current sense region, protective layers are formed, respectively. The protective layer at the boundary portion between the active region and the current sense region has a divided portion that is divided in a direction from the active region to the current sense region.

Abstract: A drift layer is formed of silicon carbide and has a first conductivity type. A trench bottom protective layer is provided on a bottom portion of a gate trench and has a second conductivity type. A depletion suppressing layer is provided between a side surface of the gate trench and the drift layer, extends from a lower portion of a body region up to a position deeper than the bottom portion of the gate trench, has the first conductivity type, and has an impurity concentration of the first conductivity type higher than that of the drift layer. The impurity concentration of the first conductivity type of the depletion suppressing layer is reduced as the distance from the side surface of the gate trench becomes larger.

Abstract: A silicon carbide semiconductor device includes: a body region of a second conductivity type provided on a drift layer of a first conductivity type; a source region of a first conductivity type provided on the body region; a source electrode connected to the source region; a gate insulating film provided on an inner surface of a trench; a gate electrode provided inside the trench with interposition of the gate insulating film; a protective layer of a second conductivity type provided below the gate insulating film; a connection layer of a second conductivity type being in contact with the protective layer and the body region; and an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

Abstract: An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

Abstract: A silicon carbide semiconductor device includes a diffusion protective layer provided below a gate insulating film, a gate line provided on an insulation film on the bottom face of a terminal trench and electrically connected to a gate electrode, the terminal trench being located more toward the outer side than the gate trench, a gate pad joined to the gate line in the terminal trench, a terminal protective layer provided below the insulation film on the bottom face of the terminal trench, and a source electrode electrically connected to a source region, the diffusion protective layer, and the terminal protective layer. The diffusion protective layer has first extensions that extend toward the terminal protective layer and that are separated from the terminal protective layer. This configuration inhibits an excessive electric field from being applied to the gate insulating film provided on the bottom face of the gate trench.

Abstract: The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.