Patents by Inventor Yutaka Funabashi

Yutaka Funabashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017824
    Abstract: An interference of control signals is caused by a deviation in the start timings of counting between counters of timer counter units of a first MCU and a second MCU. And thus, when a count value of the counter of the MCU of a parent reaches a predetermined value D, the MCU of the parent transmits a trigger signal to the MCU of a child. The MCU of the child obtains the time difference between the start timings of the counts of the counters of the parent and the child from the difference between the D and a count value E of the child at that time. A count period of the child until a maximum value of the count value is reached is adjusted by the time difference.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 25, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuji Tsuda, Yutaka Funabashi, Teruki Fukuyama
  • Publication number: 20200152248
    Abstract: An interference of control signals is caused by a deviation in the start timings of counting between counters of timer counter units of a first MCU and a second MCU. And thus, when a count value of the counter of the MCU of a parent reaches a predetermined value D, the MCU of the parent transmits a trigger signal to the MCU of a child. The MCU of the child obtains the time difference between the start timings of the counts of the counters of the parent and the child from the difference between the D and a count value E of the child at that time. A count period of the child until a maximum value of the count value is reached is adjusted by the time difference.
    Type: Application
    Filed: September 27, 2019
    Publication date: May 14, 2020
    Inventors: Tetsuji TSUDA, Yutaka FUNABASHI, Teruki FUKUYAMA
  • Publication number: 20190138671
    Abstract: In order to control the occurrence of fault with respect to each of the models belonging to different simulation environments, a simulation device includes: a simulation unit that performs a simulation on a virtual device model of a first device; a simulation unit that performs a simulation on a virtual device model of a second device that performs a process using the first device; and a fault injection control unit that injects faults into the respective virtual device models, based on a scenario list including a scenario that shows the contents and occurrence conditions of the fault with respect to the first device as well as a scenario that shows the contents and occurrence conditions of the fault with respect to the second device.
    Type: Application
    Filed: August 10, 2018
    Publication date: May 9, 2019
    Inventors: Yutaka Funabashi, Masahiro Kokubo, Hirohiko Ono
  • Publication number: 20180137022
    Abstract: Provided are an arithmetic operation device and a virtual development environment apparatus making it possible to give desirable control including desirable fault injection from a test program to a virtual device model at a desirable timing.
    Type: Application
    Filed: October 17, 2017
    Publication date: May 17, 2018
    Inventors: Yutaka FUNABASHI, Masahiro KOKUBO, Yasushi ONISHI, Takuya TAKIZAWA
  • Patent number: 9503728
    Abstract: Adopted is a decoder, in which on condition that a prediction block shown by vector information extracted from a data stream, and a decode-target block have an overlap where respective pixels overlay each other, pixel information of an already-decoded portion at a distance of an integer multiple of a vector provided by the vector information from the overlap is made a prediction signal instead of the overlap, and the prediction signal is added to difference image data taken from the data stream to generate reproduction image data. The decoder is adopted for an intra-frame decoder, a local decoder of an encoder, and the like. According to a fundamental rule concerning a repetitive pattern of an image, a pixel at a distance of an integer multiple is a like pixel, and therefore the process of decoding can be performed efficiently.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: November 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Seiji Mochizuki, Yutaka Funabashi, Junichi Kimura, Masakazu Ehama
  • Patent number: 9501879
    Abstract: A semiconductor integrated circuit has a video encoder including a motion prediction unit, a motion compensation unit, a subtraction unit, a discrete cosine transform unit, a quantization unit, an inverse quantization unit, an inverse discrete cosine transform unit, and an addition unit. The encoder divides the video signal from the camera into a plurality of partial images including the central part of the image and the peripheral part of the image according to the distance from the center of the image, and processes the partial images. A pixel processing unit coordinate-transforms coordinates of a pixel included in the central part of the image into coordinates of the peripheral part of the image, and performs a process of enlarging an object of a subject included in the central part of the image on a pixel-by-pixel basis when performing the coordinate transform.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: November 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Funabashi
  • Publication number: 20120188375
    Abstract: A semiconductor integrated circuit has a video encoder including a motion prediction unit, a motion compensation unit, a subtraction unit, a discrete cosine transform unit, a quantization unit, an inverse quantization unit, an inverse discrete cosine transform unit, and an addition unit. The encoder divides the video signal from the camera into a plurality of partial images including the central part of the image and the peripheral part of the image according to the distance from the center of the image, and processes the partial images. A pixel processing unit coordinate-transforms coordinates of a pixel included in the central part of the image into coordinates of the peripheral part of the image, and performs a process of enlarging an object of a subject included in the central part of the image on a pixel-by-pixel basis when performing the coordinate transform.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yutaka FUNABASHI
  • Publication number: 20110280305
    Abstract: Adopted is a decoder, in which on condition that a prediction block shown by vector information extracted from a data stream, and a decode-target block have an overlap where respective pixels overlay each other, pixel information of an already-decoded portion at a distance of an integer multiple of a vector provided by the vector information from the overlap is made a prediction signal instead of the overlap, and the prediction signal is added to difference image data taken from the data stream to generate reproduction image data. The decoder is adopted for an intra-frame decoder, a local decoder of an encoder, and the like. According to a fundamental rule concerning a repetitive pattern of an image, a pixel at a distance of an integer multiple is a like pixel, and therefore the process of decoding can be performed efficiently.
    Type: Application
    Filed: June 15, 2009
    Publication date: November 17, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Yutaka Funabashi, Junichi Kimura, Masakazu Ehama