Patents by Inventor Yutaka Hojyo

Yutaka Hojyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7573049
    Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 11, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
  • Publication number: 20080174779
    Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.
    Type: Application
    Filed: December 5, 2007
    Publication date: July 24, 2008
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
  • Patent number: 7323697
    Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: January 29, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
  • Publication number: 20060091321
    Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.
    Type: Application
    Filed: October 27, 2005
    Publication date: May 4, 2006
    Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
  • Patent number: 6337486
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Publication number: 20010015413
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 23, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6246064
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: June 12, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6127683
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: October 3, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 5972772
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: October 26, 1999
    Assignees: Hitachi Ltd., Hitachi Instruments Engineering Co., Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh