Patents by Inventor Yutaka Hojyo
Yutaka Hojyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7573049Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.Type: GrantFiled: December 5, 2007Date of Patent: August 11, 2009Assignee: Hitachi High-Technologies CorporationInventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
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Publication number: 20080174779Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.Type: ApplicationFiled: December 5, 2007Publication date: July 24, 2008Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
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Patent number: 7323697Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.Type: GrantFiled: October 27, 2005Date of Patent: January 29, 2008Assignee: Hitachi High-Technologies CorporationInventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
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Publication number: 20060091321Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.Type: ApplicationFiled: October 27, 2005Publication date: May 4, 2006Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
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Patent number: 6337486Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.Type: GrantFiled: April 30, 2001Date of Patent: January 8, 2002Assignee: Hitachi, Ltd.Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
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Publication number: 20010015413Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.Type: ApplicationFiled: April 30, 2001Publication date: August 23, 2001Applicant: Hitachi, Ltd.Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
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Patent number: 6246064Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be with a high throughput and with a high accuracy without any manual adjustment.Type: GrantFiled: June 29, 2000Date of Patent: June 12, 2001Assignee: Hitachi, Ltd.Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
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Patent number: 6127683Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.Type: GrantFiled: September 15, 1999Date of Patent: October 3, 2000Assignee: Hitachi, Ltd.Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
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Patent number: 5972772Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.Type: GrantFiled: September 3, 1997Date of Patent: October 26, 1999Assignees: Hitachi Ltd., Hitachi Instruments Engineering Co., Ltd.Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh