Patents by Inventor Yutaka IGAKU
Yutaka IGAKU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10761139Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.Type: GrantFiled: November 5, 2018Date of Patent: September 1, 2020Assignee: Renesas Electronics CorporationInventors: Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
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Patent number: 10576968Abstract: A control system 9 according to the present invention is mounted on a moving object. The control system 9 includes: an observing device 92 which transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction device 91 which transmits first control data indicating the control contents determined based on the observation result data; a movement control device 93 which controls movement of the moving object; and a relay device 95 which relays the first control data transmitted from the first control instruction device 91, to the movement control device 93. When a second control instruction device 94 which transmits second control data indicating the control contents determined based on the observation result data is provided to the control system 9, the relay device 95 transmits the second control data instead of the first control data, to the movement control device 93.Type: GrantFiled: June 28, 2017Date of Patent: March 3, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Yamakoshi, Yukitoshi Tsuboi, Yutaka Igaku
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Patent number: 10520549Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.Type: GrantFiled: November 1, 2017Date of Patent: December 31, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
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Publication number: 20190072611Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.Type: ApplicationFiled: November 5, 2018Publication date: March 7, 2019Inventors: Shinichi SHIBAHARA, Daisuke KAWAKAMI, Yutaka IGAKU
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Patent number: 10151796Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.Type: GrantFiled: April 8, 2016Date of Patent: December 11, 2018Assignee: Renesas Electronics CorporationInventors: Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
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Publication number: 20180080984Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.Type: ApplicationFiled: November 1, 2017Publication date: March 22, 2018Inventors: Yukitoshi TSUBOI, Hideo NAGANO, Hiroshi NAGAOKA, Yusuke MATSUNAGA, Yutaka IGAKU, Naotaka KUBOTA
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Patent number: 9810738Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.Type: GrantFiled: April 1, 2015Date of Patent: November 7, 2017Assignee: Renesas Electronics CorporationInventors: Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
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Publication number: 20170297570Abstract: A control system 9 according to the present invention is mounted on a moving object. The control system 9 includes: an observing device 92 which transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction device 91 which transmits first control data indicating the control contents determined based on the observation result data; a movement control device 93 which controls movement of the moving object; and a relay device 95 which relays the first control data transmitted from the first control instruction device 91, to the movement control device 93. When a second control instruction device 94 which transmits second control data indicating the control contents determined based on the observation result data is provided to the control system 9, the relay device 95 transmits the second control data instead of the first control data, to the movement control device 93.Type: ApplicationFiled: June 28, 2017Publication date: October 19, 2017Applicant: Renesas Electronics CorporationInventors: Yasuhiro YAMAKOSHI, Yukitoshi TSUBOI, Yutaka IGAKU
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Patent number: 9725088Abstract: A control system 9 according to the present invention is mounted on a moving object. The control system 9 includes: an observing device 92 which transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction device 91 which transmits first control data indicating the control contents determined based on the observation result data; a movement control device 93 which controls movement of the moving object; and a relay device 95 which relays the first control data transmitted from the first control instruction device 91, to the movement control device 93. When a second control instruction device 94 which transmits second control data indicating the control contents determined based on the observation result data is provided to the control system 9, the relay device 95 transmits the second control data instead of the first control data, to the movement control device 93.Type: GrantFiled: August 6, 2015Date of Patent: August 8, 2017Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yamakoshi, Yukitoshi Tsuboi, Yutaka Igaku
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Publication number: 20160349322Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.Type: ApplicationFiled: April 8, 2016Publication date: December 1, 2016Inventors: Shinichi SHIBAHARA, Daisuke KAWAKAMI, Yutaka IGAKU
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Publication number: 20160059853Abstract: A control system 9 according to the present invention is mounted on a moving object. The control system 9 includes: an observing device 92 which transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction device 91 which transmits first control data indicating the control contents determined based on the observation result data; a movement control device 93 which controls movement of the moving object; and a relay device 95 which relays the first control data transmitted from the first control instruction device 91, to the movement control device 93. When a second control instruction device 94 which transmits second control data indicating the control contents determined based on the observation result data is provided to the control system 9, the relay device 95 transmits the second control data instead of the first control data, to the movement control device 93.Type: ApplicationFiled: August 6, 2015Publication date: March 3, 2016Applicant: Renesas Electronics CorporationInventors: Yasuhiro YAMAKOSHI, Yukitoshi TSUBOI, Yutaka IGAKU
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Publication number: 20150293173Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.Type: ApplicationFiled: April 1, 2015Publication date: October 15, 2015Inventors: Yukitoshi TSUBOI, Hideo NAGANO, Hiroshi NAGAOKA, Yusuke MATSUNAGA, Yutaka IGAKU, Naotaka KUBOTA