Patents by Inventor Yutaka Kagaya
Yutaka Kagaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240137075Abstract: A reflect array that sets a reflection angle of a radio wave to an angle that is different from an angle of specular reflection. The reflect array includes a plurality of cells arranged in an array. Each of the plurality of cells includes at least two main resonant elements and a parasitic resonant element coupled to the at least two main resonant elements. The parasitic resonant element is configured to adjust a resonant frequency of the parasitic resonant element and adjust a reflection phase of a surface of the reflect array by adjusting a resonant frequency of the at least two main resonant elements each adjacent to the parasitic resonant element, to which the parasitic resonant element is coupled.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: AGC Inc.Inventors: Akira KUMAGAI, Kotaro ENOMOTO, Osamu KAGAYA, Yutaka UI
-
Patent number: 11069655Abstract: A semiconductor device includes a composite chip mounted over a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. The first area includes a first circuit formed in the first area, and the second area includes a second circuit formed in the second area. The first area is spaced apart from the second area by the first material.Type: GrantFiled: November 17, 2017Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Sensho Usami, Kazuhiko Shibata, Yutaka Kagaya
-
Publication number: 20210035898Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate having a first surface and a second surface opposite to each other, a die electrically coupled to the substrate, an encapsulant disposed over the first surface of the substrate to encapsulate the die, at least one first conductive terminal and at least one second conductive terminal. The at least one first conductive terminal and the at least one second conductive terminal are disposed on the second surface of the substrate. The at least one second conductive terminal is electrically connected to the die through the substrate. The at least one first conductive terminal is overlapped with the die in a direction perpendicular to the second surface of the substrate. A first area of the at least one first conductive terminal is larger than a second area of the at least one second conductive terminal.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Applicant: Powertech Technology Inc.Inventor: Yutaka Kagaya
-
Publication number: 20180076173Abstract: A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area. The first area is spaced apart from the second area by the first material.Type: ApplicationFiled: November 17, 2017Publication date: March 15, 2018Inventors: Sensho Usami, Kazuhiko Shibata, Yutaka Kagaya
-
Patent number: 9837377Abstract: A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.Type: GrantFiled: October 21, 2014Date of Patent: December 5, 2017Assignee: Micron Technology, Inc.Inventors: Sensho Usami, Kazuhiko Shibata, Yutaka Kagaya
-
Patent number: 9252125Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: GrantFiled: July 2, 2012Date of Patent: February 2, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
-
Publication number: 20150108637Abstract: A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.Type: ApplicationFiled: October 21, 2014Publication date: April 23, 2015Inventors: Sensho Usami, Kazuhiko Shibata, Yutaka Kagaya
-
Patent number: 8710647Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.Type: GrantFiled: October 17, 2011Date of Patent: April 29, 2014Inventors: Yutaka Kagaya, Fumitomo Watanabe, Hajime Takasaki
-
Patent number: 8524890Abstract: The invention has for its object to provide a water-soluble phthalocyanine dye unlikely to lose its own properties even upon dissolved in a concentration as high as 10?5 M. The inventive water-soluble phthalocyanine dye is characterized by having a sulfuric acid group or groups as an axial ligand or ligands of an antimony/phthalocyanine complex. The sulfuric acid group or groups have been introduced by replacing a part or the whole of hydroxyl groups in the starting material with a sulfuric acid group or groups.Type: GrantFiled: February 24, 2010Date of Patent: September 3, 2013Assignee: National Institute for Materials ScienceInventors: Hiroaki Isago, Yutaka Kagaya, Youichi Oyama, Harumi Fujita
-
Publication number: 20130001755Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: ApplicationFiled: July 2, 2012Publication date: January 3, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka KAGAYA, Hidehiro TAKESHIMA, Masamichi ISHIHARA
-
Patent number: 8247896Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: GrantFiled: September 3, 2010Date of Patent: August 21, 2012Assignee: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
-
Publication number: 20120032353Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.Type: ApplicationFiled: October 17, 2011Publication date: February 9, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka KAGAYA, Fumitomo WATANABE, Hajime TAKASAKI
-
Patent number: 8076770Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.Type: GrantFiled: August 12, 2008Date of Patent: December 13, 2011Assignee: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Fumitomo Watanabe, Hajime Takasaki
-
Publication number: 20110301344Abstract: The invention has for its object to provide a water-soluble phthalocyanine dye unlikely to lose its own properties even upon dissolved in a concentration as high as 10?5 M. The inventive water-soluble phthalocyanine dye is characterized by having a sulfuric acid group or groups as an axial ligand or ligands of an antimony/phthalocyanine complex. The sulfuric acid group or groups have been introduced by replacing a part or the whole of hydroxyl groups in the starting material with a sulfuric acid group or groups. See FIG. 4.Type: ApplicationFiled: February 24, 2010Publication date: December 8, 2011Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCEInventors: Hiroaki Isago, Yutaka Kagaya, Youichi Oyama, Harumi Fujita
-
Patent number: 7935576Abstract: Semiconductor device 10 includes wiring substrate 11 including wiring 14 and wiring 15 in predetermined patterns, semiconductor chips 19 and 23 which are mounted on wiring substrate 11 with electrodes electrically connected to wiring 14 of wiring substrate 11 via wires 21 and 24, first sealing body 25 made of an insulative resin which is formed on a part of wiring substrate 11 and which covers semiconductor chips 19 and 23 and wires 21 and 24, a plurality of connecting connection pads 27 provided on the top surface of first sealing body 25, a plurality of connecting wires 26 which extend from the surface of wiring substrate 11, on which semiconductor chips 19 and 23 are mounted, to the top surface of first sealing body 25 via the side surfaces of first sealing body 25, and which electrically connect wiring 14 of wiring substrate 11 and the plurality of connecting connection pads 27 and second sealing body 28 made of an insulative resin which covers the plurality of connecting wires 26.Type: GrantFiled: October 14, 2008Date of Patent: May 3, 2011Assignee: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Hidehiro Takeshima
-
Patent number: 7888179Abstract: The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part.Type: GrantFiled: August 5, 2008Date of Patent: February 15, 2011Assignee: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Fumitomo Watanabe
-
Publication number: 20110001235Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: ApplicationFiled: September 3, 2010Publication date: January 6, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka KAGAYA, Hidehiro TAKESHIMA, Masamichi ISHIHARA
-
Patent number: 7808093Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: GrantFiled: April 11, 2007Date of Patent: October 5, 2010Assignee: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
-
Publication number: 20090096097Abstract: Semiconductor device 10 includes wiring substrate 11 including wiring 14 and wiring 15 in predetermined patterns, semiconductor chips 19 and 23 which are mounted on wiring substrate 11 with electrodes electrically connected to wiring 14 of wiring substrate 11 via wires 21 and 24, first sealing body 25 made of an insulative resin which is formed on a part of wiring substrate 11 and which covers semiconductor chips 19 and 23 and wires 21 and 24, a plurality of connecting connection pads 27 provided on the top surface of first sealing body 25, a plurality of connecting wires 26 which extend from the surface of wiring substrate 11, on which semiconductor chips 19 and 23 are mounted, to the top surface of first sealing body 25 via the side surfaces of first sealing body 25, and which electrically connect wiring 14 of wiring substrate 11 and the plurality of connecting connection pads 27 and second sealing body 28 made of an insulative resin which covers the plurality of connecting wires 26.Type: ApplicationFiled: October 14, 2008Publication date: April 16, 2009Applicant: Elpida Memory, Inc.Inventors: Yutaka Kagaya, Hidehiro Takeshima
-
Publication number: 20090045497Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.Type: ApplicationFiled: August 12, 2008Publication date: February 19, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka KAGAYA, Fumitomo WATANABE, Hajime TAKASAKI