Patents by Inventor Yutaka KIRIHATA
Yutaka KIRIHATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9419168Abstract: A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.Type: GrantFiled: September 5, 2014Date of Patent: August 16, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masato Nakasu, Naoya Sotani, Yutaka Kirihata
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Patent number: 9257593Abstract: There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer (16) and an n-type amorphous silicon layer (14) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate (18); a second step in which an i-type amorphous silicon layer (22a) and an n-type amorphous silicon layer (23a) are formed over a back surface of the n-type monocrystalline silicon substrate (18); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer (14) and the n-type amorphous silicon layer (23a).Type: GrantFiled: September 17, 2013Date of Patent: February 9, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Taiki Hashiguchi, Yutaka Kirihata
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Patent number: 9196780Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a second amorphous semiconductor layer placed on another region of the substrate and being of another conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided above the first amorphous semiconductor layer, a third amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of the other conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, and a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type.Type: GrantFiled: December 24, 2014Date of Patent: November 24, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yutaka Kirihata, Masato Nakasu, Naoya Sotani
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Patent number: 9070822Abstract: The method disclosed herein includes a first step of forming an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 on a light-receiving surface of an n-type monocrystalline silicon substrate 18; a second step of forming an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a on a backside surface of the n-type monocrystalline silicon substrate 18; and a third step of forming, after completion of the first step and the second step, an antireflection layer 12 on the n-type amorphous silicon layer 14, and subsequently forming an insulating layer 24a on the n-type amorphous silicon layer 23a.Type: GrantFiled: September 25, 2013Date of Patent: June 30, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yutaka Kirihata, Taiki Hashiguchi
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Publication number: 20150114465Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a second amorphous semiconductor layer placed on another region of the substrate and being of another conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided above the first amorphous semiconductor layer, a third amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of the other conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, and a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type.Type: ApplicationFiled: December 24, 2014Publication date: April 30, 2015Inventors: Yutaka KIRIHATA, Masato NAKASU, Naoya SOTANI
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Publication number: 20150107668Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided to extend from another region of the substrate over onto the first amorphous semiconductor layer, a second amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of another conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type, and a third amorphous semiconductor layer placed between the second crystalline semiconductor layer and the i-type amorphous semiconductor layer and being ofType: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Inventors: Naoya SOTANI, Masato NAKASU, Yutaka KIRIHATA
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Publication number: 20140024167Abstract: The method disclosed herein includes a first step of forming an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 on a light-receiving surface of an n-type monocrystalline silicon substrate 18; a second step of forming an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a on a backside surface of the n-type monocrystalline silicon substrate 18; and a third step of forming, after completion of the first step and the second step, an antireflection layer 12 on the n-type amorphous silicon layer 14, and subsequently forming an insulating layer 24a on the n-type amorphous silicon layer 23a.Type: ApplicationFiled: September 25, 2013Publication date: January 23, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Yutaka KIRIHATA, Taiki HASHIGUCHI
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Publication number: 20140020756Abstract: A photovoltaic device (10) is provided with: an n-type monocrystalline silicon substrate (21); an IN layer (25) layered over one surface of the n-type monocrystalline silicon substrate (21); an IP layer (26) layered over a region, of one surface of the IN layer 25, where the IN layer (25) is not layered, and layered so as to have an overlap region (26*) which is overlapped with the region where the IN layer (25) is layered; an n-side electrode (40) electrically connected to the IN layer (25) and formed over the overlap region (26*); and a p-side electrode (50) formed distanced from the n-side electrode (40) and electrically connected to the IP layer (26). In the IP layer (26), a separation gap (60) is formed between a region where the n-side electrode (40) is formed and a region where the p-side electrode (50) is formed.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Ryo GOTO, Taiki HASHIGUCHI, Kazunori FUJITA, Masato SHIGEMATSU, Yutaka KIRIHATA, Takahiro MISHIMA
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Publication number: 20140017850Abstract: There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer (16) and an n-type amorphous silicon layer (14) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate (18); a second step in which an i-type amorphous silicon layer (22a) and an n-type amorphous silicon layer (23a) are formed over a back surface of the n-type monocrystalline silicon substrate (18); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer (14) and the n-type amorphous silicon layer (23a).Type: ApplicationFiled: September 17, 2013Publication date: January 16, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Taiki HASHIGUCHI, Yutaka KIRIHATA