Patents by Inventor Yutaka Koma

Yutaka Koma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6511895
    Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 28, 2003
    Assignees: Disco Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
  • Publication number: 20020173244
    Abstract: A polishing tool comprising a support member, and polishing means fixed to the support member. The polishing means is composed of felt having a density of 0.20 g/cm3 or more and a hardness of 30 or more, and abrasive grains dispersed in the felt. A polishing method and apparatus involving pressing the polishing means against a surface of a workpiece to be polished, while rotating the workpiece and also rotating the polishing tool.
    Type: Application
    Filed: March 20, 2002
    Publication date: November 21, 2002
    Inventors: Sinnosuke Sekiya, Setsuo Yamamoto, Yutaka Koma, Masashi Aoki, Naohiro Matsuya
  • Patent number: 6343980
    Abstract: Three columns 10, 20, 30 are set up in an approximately triangle arrangement. A saddle 51, which fixes a main spindle 50 thereto, is held in contact with a side face of the column 10, 20 or 30 or a brace 40 which unitarily connects two or three of the columns 10, 20, 30. A plurality of chucking tables 4a, 4b are installed in an indexing table 2a. When a work piece 5b attracted onto one chucking table 4b is carried to a position below the main spindle 50, the other chucking table 4a is located at a loading-unloading position. Since the main spindle 50 is located at a geometrical gravity center of a triangle defined by the columns 10, 20, 30, a reaction force which is generated during machining is uniformly distributed to each of the columns 10, 20, 30. Consequently, the columns 10, 20, 30 are prevented from deformation which causes inclination of the main spindle 50, and the machined work piece has superior flatness.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: February 5, 2002
    Assignees: Supersilicon Crystal Research Institute Corporation, Disco Corporation
    Inventors: Kohzo Abe, Yutaka Koma
  • Publication number: 20010021571
    Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.
    Type: Application
    Filed: February 26, 2001
    Publication date: September 13, 2001
    Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
  • Patent number: 6159071
    Abstract: Disclosed is an improved semiconductor wafer grinding apparatus comprising at least wafer holding means and wafer grinding means. The wafer holding means comprises a holder having a wafer-gripping surface for sucking and holding a selected semiconductor wafer and liquid bearing means for rotatably supporting the holder. The liquid bearing means has inclination control means formed therein, and the inclination control means includes discrete inclination controlling areas for suspending the holder at upper and lower levels. Each inclination controlling area has flow rate control means connected thereto. The parallelism of the wafer-gripping surface relative to the wafer grinding means is assured by controlling the flow rate of the liquid to each inclination controlling area.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: December 12, 2000
    Assignee: Disco Corporation
    Inventors: Yutaka Koma, Motomi Kitano, Takashi Kouda