Abstract: A display device includes: a display area including partial display areas; sub-pixels, each sub-pixel including a memory block with memories to store sub-pixel data; memory selection line groups, each of which is provided in each row or column in each partial display area and includes memory selection lines, each memory selection line electrically being coupled to the memory blocks, each of which belongs to the sub-pixels arranged in the row or the column; a memory selection control circuit for one of the memory selection lines from each memory selection line group, the memory selection lines selected functioning as an output destination of a memory selection signal for selecting one of the memories in the memory block; a memory selection circuit outputting the memory selection signal; and distribution circuits outputting the memory selection signal to the selected one of the memory selection lines in each memory selection line group.

Abstract: According to an aspect, a display device includes: sub-pixels arranged in row and column directions and each including a memory block including memories to store therein sub-pixel data; memory selection line groups corresponding to rows and each including memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row; and a memory selection circuit configured to concurrently output a memory selection signal to the memory selection line groups. Each sub-pixel displays an image based on the sub-pixel data stored in one of the memories in accordance with the memory selection line supplied with the memory selection signal. The number of times that the set value is changed is less than the number of times that images are switched from one to another based on the memory selection signal output from the memory selection circuit.

Abstract: A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

Abstract: A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.

Abstract: A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.