Abstract: To increase the kinds of executable instructions of a microcomputer without increasing the number of bits (e.g. 8 bits) constituting one word or instruction, that is, without decreasing the execution speed or increasing the ROM usage, two or more instruction groups including instructions of different kinds, respectively, are provided operation modes are determined for the respective instruction groups; and the respective instruction groups to be executed are switched according to the respective operation modes. The microcomputer includes an instruction register, an execution control unit, a mode memory flip-flop, gates, two predecoders, a programmable logic array, an arithmetic logic unit, etc. The ordinary and special instruction groups can be selected in response to an interrupt entry signal and an interrupt return signal and a specific bit of an instruction, for instance.

Abstract: On a single chip microprocessor which has 2.sup.n operation modes, apparatus which permits selecting one mode out of the 2.sup.n operation modes by using only one external pin connection and user program execution. A mode-setting register on the single chip microprocessor can be updated both through the external pin designating one of the two start modes, which are part of the 2.sup.n operation modes, during the reset state of the microprocessor and through a write operation generated by executing a user program during the normal (nonreset) state of the microprocessor.

Abstract: An A-D converter for converting into a pulse train signal an analog input voltage signal from a signal source, said A-D converter comprising a signal generator for providing a low analog input voltage signal of a low fixed level V.sub.L, a signal generator for providing a high analog input voltage signal of a high fixed level V.sub.

Abstract: A data processing system is disclosed which includes a memory having a plurality of addressable register banks and for memory areas for performing a re-entrant function of a subroutine. The memory areas store a start address of an interrupt program, a program status word of the interrupt program, and a register bank pointer code to be used by the interrupt program. The memory has a program counter, a program status word, and a register bank pointer. When an interrupt request is received, the contents of a program counter, the program status word, and the register bank pointer are swapped with the contents of a particular memory area group. Further, by swapping the contents of the program counter with the contents of the register in the register bank which contains in advance the start address of the subroutine to be used, the re-entrant operation of the subroutine may be accomplished.

Abstract: An output control device for an internal combustion engine has a plurality of registers connected to a data bus. These registers comprise registers for holding output request time data specifying when the generation of output signals will be requested, and mask data specifying whether the registers are reserved for output operations or may be used as working RAM. Other registers are provided for holding output request time data, mask data, and channel designating data specifying the output channel on which output signals will be generated. Unloading of the data in these registers is performed by sequentially supplying gate switching control signals from a shifter to gates connected to these registers. The output request time data is compared with absolute time data from a timer by a comparator, and a coincidence signal indicating coincidence detection is applied to a mask gate together with the mask data. Whether to accept the coincidence data or not is determined according to the value of the mask data.

Abstract: The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of a groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

Abstract: The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.