Abstract: A controller capable of monitoring a receiving circuit for receiving machine information. Machine information from a machine is received by a plurality of independent systems and the external signals received by the plurality of systems are compared, thereby, a receiving state of the receiving circuit is monitored. The controller includes a plurality of independent receiving units for receiving the external signal and monitoring units for comparing signals received by the plurality of receiving units, to monitor the receiving units based on a result of the comparison.

Abstract: A controller for an industrial machine capable of monitoring a receiving circuit for receiving position information. A receiving circuit and an additional receiving circuit receive the same position information from a detector, and a monitoring circuit monitors a receiving state of the receiving circuit using position information received by the additional receiving circuit. A plurality of receiving circuits may be provided for respectively receiving different position information, and a plurality of additional receiving circuits and a plurality of monitoring circuits may be provided in a manner such that each additional receiving circuit and each monitoring circuit is associated with each receiving circuit. A single additional receiving circuit and a single monitoring circuit may be common to a plurality of receiving circuits.

Abstract: A casing structure for a numerical control unit in which a cooling fan mounted on a fan cover is electrically connected with a control board attached to a main cover without using cables. A terminal unit connected with wiring of a fan motor is fixed to a fan cover, and a power supply terminal to be directly connected with the terminal unit is fixed to an upper end portion of a main control board The terminal unit is connected with or disconnected from the power supply terminal by attaching or detaching the fan cover to or from a casing body. Since cables are not needed for connection, a casing can be assembled and disassembled easily. Further, since an assembling error due to interference of cables is eliminated, automation of the assembling work can be easily achieved.

Abstract: An image processing apparatus is constructed by providing in parallel a plurality of dyadic look-up tables (10, 20) to which plural items of image data (I1, I2) read out of respective image memories (40, 50) are inputted. The dyadic look-up tables output data corresponding to a prescribed function, and provide this data to an image arithmetic (30) unit, which executes an operation corresponding to the prescribed function.

Abstract: A picture processing apparatus inputs window data (W) to look-up tables (TBL) in which operators (G or F) to be applied to pixel data (x) are stored in correlation to the locations of the pixel data. By switching between the operators (G or F) contained in the look-up tables (TBL), window processing corresponding to a data address (i,j) is performed on input pixel data (x.sub.ij).

Abstract: A system for calculation of a sum of products is provided in which an inexpensive sum-of-products arithmetic unit is utilized. When n/d processors of a processor array (2) are input with individual data items in a data sequence from a memory (1), the data items are multiplied by set coefficients of n coefficients. An output equal to the sum of the products obtained is added by an adder (3) to a stored value which is read from a corresponding address of an intermediate storage unit (4), and the sum obtained is stored in the intermediate storage unit. The input data is then shifted, and the process described above is again executed. When the process is completed for all the data sequence in the memory (1), the above-described operation is again performed, with the reading of data from the intermediate storage (4) and writing of the output of the adder delayed by n/d cycles and with other coefficients of the n coefficients being set.

Abstract: A device for calculating the moments of image data has a plurality of image frame memories. The device has an image frame memory (12) for storing original image data, an image frame memory (13) for storing processed data, and image frame memories (13, 14) for storing weight data in includes an adder(7) for processing the data stored in these memories, a multiplier (6) for multiplying the data in the image frame memories, and an accumulator (8) for temporarily storing calculating results. These memories and the arithmetic units such as the adder (7) and other serve to calculate the zero-order, primary, and secondary moments of image data.

Abstract: A picture processing apparatus uses coefficient matrix data to perform convolution processing on a time-sharing basis with regard to each item of pixel data of a frame memory (3) which stores plural items of pixel data. When such processing is being performed, the results of addition from the adder (5) are delayed a predetermined period of time by delay device (7), thereby assuring that intermediate processing results may be written in the buffer (9) with certainty. At the same time, a read-out address of the buffer (9) is revised by an amount equivalent to the delay in the write timing, thereby making it possible to speed up the time-sharing convolution processing.

Abstract: The present invention is directed to a picture processing apparatus for painting a picture memory of a CRT display unit or similar apparatus by paint data. In accordance with this picture processing apparatus, a dual-port memory (4) is used as a frame buffer for storing picture information. In order to store paint information in a memory cell array (7), the information is internally transferred from predetermined storage circuit (9) via a data register (8) having a serial input function. The number of times the dual-port memory (4) is accessed from the processor (1) is greatly reduced so that the burden on the processor (1) can be alleviated. It is also possible to shorten the time required for the paint information to be stored in the memory cell array (7).

Abstract: In a picture processing apparatus, a front porch time (FP) conforming to a picture signal from a particular picture input unit (2) is stored beforehand in a register (R) by a host computer (8). When the picture input unit (2) outputs a horizontal synchronizing signal (HSYNC), the front porch time (FP) from issuance of the horizontal synchronizing signal (HSYNC) until the beginning of a significant picture information interval (PCPD) is calculated by referring to the register (R) and counting down the value from the register. The picture information is then introduced into a picture memory (6) from the calculated beginning of the significant picture information interval (PCPD). The picture processing apparatus may be used for a variety of different picture input units, as the host computer stores the front porch time corresponding to the particular picture input unit to be used in the register (R) prior to picture processing.