Abstract: A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.

Abstract: A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, wherei

Abstract: A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.

Abstract: A relay device receives packets from an information processing apparatus or a relay device. The relay device updates a value of priority data indicating an accumulated wait time for arbitration contained in each of the received packets according to an elapsed time. The relay device selects a packet to be transmitted according to a result of comparison of the values of the pieces of the priority data contained in the received packets. The relay device transmits the selected packet to another relay device.

Abstract: A transmission system includes a data sending device that sends data at a first speed and a data receiving device that receives, by using a plurality of clocks having different phases, data that has been sent by the sending device at the first speed. The data sending device sends, to the data receiving device, some of the data, which is sent at the first speed, at a second speed that is lower than the first speed. Furthermore, in accordance with determination as to whether the content of the received data sent at the second speed matches a corresponding portion of the data received by using a plurality of clocks, the data receiving device changes the timing at which the data that has been sent at the first speed is received.

Abstract: A data transmission system includes a plurality of signal lines, a signal line determination unit, and a data transmission unit. The plurality of signal lines transmit data transmitted from a transmission-side device to a reception-side device. The signal line determination unit determines which signal line among the signal lines is used to transmit reception adjustment data to the reception-side device. The data transmission unit uses the signal line determined by the signal line determination unit to transmit the reception adjustment data to the reception-side device and uses another signal line to transmit transmission data to the reception-side device.

Abstract: A system includes a transmitting device configured to transmit a packet, and a receiving device connected through a switch device to the transmitting device, the receiving device being configured to receive the packet, wherein the switch device includes a first memory storing first expected value information indicative of an expected value of a fixed value region, the fixed value region being a region whose value is determined in advance in a transaction layer packet, and a switch control unit configured to compare a value of the fixed value region of the transaction layer packet received from the transmitting device with the expected value and make an error response to the transmitting device if the value of the fixed value region is different from the expected value.

Abstract: A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.

Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

Abstract: An attachment structure includes a bracket that is arranged around a steering, a rotary connector device that has an engagement portion for being provisionally fixed to the bracket in a provisionally fixed state, and a combination switch that has a guide portion for being slidably retained to the bracket in the provisionally fixed state. The rotary connector device and the combination switch are completely fastened together with the bracket by a screw member from the provisionally fixed state.

Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

Abstract: An attachment structure includes a bracket that is arranged around a steering, a rotary connector device that has an engagement portion for being provisionally fixed to the bracket in a provisionally fixed state, and a combination switch that has a guide portion for being slidably retained to the bracket in the provisionally fixed state. The rotary connector device and the combination switch are completely fastened together with the bracket by a screw member from the provisionally fixed state.

Abstract: In a switch device including: a push button disposed in an opening of a switch case and operable to be tilted in any one of a plurality of directions by being pushed at an outer edge side; a rubber contact that forces the push button to a position before pushing; and a movable contact and a fixed contact connectable to each other by each pushing operation on the push button, a convex portion and a concave portion that can be spaced apart from each other are separately provided to the push button and the switch case for rotational support and positional regulation of the push button with respect to the switch case at the time of a tilting operation by each pushing.

Abstract: A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.

Abstract: A vehicle status change-over device is disclosed wherein an ignition switch 4 and a case 5 are fixed to a steering column cover, a case 5 supports a rotator 6 for rotational movement while fixing a shift position switch 8, a dial 9 is mounted to the case 5 for rotational movement about a center on substantially the line as a rotational center of the rotator 6, a shift lock solenoid 15 is mounted to an outer periphery of the case 5 at an area corresponding to a bore 14, and a lock pin 6 is provided to be moveable with the shift lock solenoid 15.

Abstract: In a switch device including: a push button disposed in an opening of a switch case and operable to be tilted in any one of a plurality of directions by being pushed at an outer edge side; a rubber contact that forces the push button to a position before pushing; and a movable contact and a fixed contact connectable to each other by each pushing operation on the push button, a convex portion and a concave portion that can be spaced apart from each other are separately provided to the push button and the switch case for rotational support and positional regulation of the push button with respect to the switch case at the time of a tilting operation by each pushing.

Abstract: A vehicle status change-over device is disclosed wherein an ignition switch 4 and a case 5 are fixed to a steering column cover, a case 5 supports a rotator 6 for rotational movement while fixing a shift position switch 8, a dial 9 is mounted to the case 5 for rotational movement about a center on substantially the line as a rotational center of the rotator 6, a shift lock solenoid 15 is mounted to an outer periphery of the case 5 at an area corresponding to a bore 14, and a lock pin 6 is provided to be moveable with the shift lock solenoid 15.

Abstract: The invention provides a waterproof switch which can electrically open and close an door of a vehicle body by a switch, can achieve a seal between a waterproof switch and a panel and a seal against an inner portion of the waterproof switch by one seal member, and previously make a seal member hold in a side of the waterproof switch at a time of assembling.