Abstract: A bus bar unit is configured to supply power to coils (16) of a plurality of phases, and includes phase bus bars (47U ), (47V), and (47W) which are provided for each phase and are connected to winding start ends of the coils, and a neutral point bus bar (81) which is connected to winding finish ends of the coils, the neutral point bus bar (81) being formed by bending an elongated plate-shaped member such that a width direction of the elongated plate-shaped member and a radial direction of the bus bar unit coincide with each other, and including a plurality of bus bar pieces (82) and a connection portion (83) which connects the bus bar pieces (82) and (82) adjacent to each other, and a width of a deformation portion (85) of the connection portion (83) being narrower than a width of the bus bar piece (82).

Abstract: The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal.

Abstract: In LSI circuit devices having a plurality of subchips packaged therein and having specific functions, capacitance cutting buffer circuits are employed in conjunction with respective terminals of the subchips, and a driver is disposed at respective points where relatively long wiring lines are respectively sub-divided into a corresponding plurality of lines. As a result, signal transmission delay can be significantly reduced. The terminals of the subchips are also provided with a probing pad to test the operations of the subchips independently of one another. The subchips employ circuit blocks which are to operate simultaneously and in conjunction with the wirings of the subchips, power supply lines are disposed correspondingly to the distributively arranged circuit blocks. Bus lines also controllably transmit addresses as well as data signals in a time sharing manner. Furthermore, each of the subchips has a fault test circuit.

Abstract: There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse.

Abstract: A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.