Abstract: According to one embodiment, a device includes: a memory cell between the first and second interconnects; a first circuit in a domain having a range of a first voltage to a second voltage higher than the first voltage, the first circuit controlling supply of the second voltage to the first interconnect; a second circuit in a domain having a range of a third voltage lower than the first voltage to the first voltage, the second circuit controlling supply of the third voltage to the second interconnect; and a third circuit in a domain having a range of a fourth voltage lower than the first voltage to a fifth voltage higher than the first voltage, the third circuit controlling supply of a sixth voltage to the first and second interconnects.

Abstract: An imaging apparatus includes a first communicator, a second communicator, a setter, and a controller. The first communicator performs first communication with an external device. The second communicator performs second communication with the external device. The setter sets a first function or a second function as a function when remotely activated from the external device. The first function includes a function of transmitting image data to the external device via the first communicator and receiving an operation signal for remote control from the external device. The second function includes a function of receiving the operation signal from the external device via the second communicator. The controller establishes a first connection of the first communication when remotely activated from the external device in a case where the first function is set. The controller establishes a second connection of the second communication after the first connection.

Abstract: According to one embodiment, a device includes: a memory cell between the first and second interconnects; a first circuit in a domain having a range of a first voltage to a second voltage higher than the first voltage, the first circuit controlling supply of the second voltage to the first interconnect; a second circuit in a domain having a range of a third voltage lower than the first voltage to the first voltage, the second circuit controlling supply of the third voltage to the second interconnect; and a third circuit in a domain having a range of a fourth voltage lower than the first voltage to a fifth voltage higher than the first voltage, the third circuit controlling supply of a sixth voltage to the first and second interconnects.

Abstract: An imaging apparatus includes a first communicator, a second communicator, a setter, and a controller. The first communicator performs first communication with an external device. The second communicator performs second communication with the external device. The setter sets a first function or a second function as a function when remotely activated from the external device. The first function includes a function of transmitting image data to the external device via the first communicator and receiving an operation signal for remote control from the external device. The second function includes a function of receiving the operation signal from the external device via the second communicator. The controller establishes a first connection of the first communication when remotely activated from the external device in a case where the first function is set. The controller establishes a second connection of the second communication after the first connection.

Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.

Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.

Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: Disclosed is an electronic device including a semiconductor memory. The semiconductor memory includes a bit line, a source line, a plurality of resistive memory cells among which a selected resistive memory cell forms a current path between the bit line and the source line, a sense amplifier suitable for sensing data of the bit line in an active operation, a latch suitable for latching data sensed by the sense amplifier in the active operation, a write control unit suitable for comparing data latched in the latch with write data in a write operation, and a write driver suitable for driving the bit line and the source line based on a comparison result of the write control unit and the write data in the write operation.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer.

Abstract: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or non-selected, based on an input signal. They also include an address signal input section configured to provide a signal to address the memory chip, based on an input signal. They further include a select address signal input section configured to make the plurality of memory chips selected or non-selected, based on an input signal, and configured divertible to the address signal input section.

Abstract: A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer.

Abstract: A semiconductor memory device includes a nonvolatile memory functioning as a main memory unit, a volatile memory functioning as a buffer unit of the nonvolatile memory, a controller, an ECC buffer, a parity syndrome circuit, an ECC control circuit, a multiplexer, and an ECC error position decoder.

Abstract: An error-correcting system includes a data buffer, a generating unit, a syndrome holding unit, a parity holding unit, and a decoding unit. The data buffer is capable of holding N bits of data. The generating unit generates a syndrome and parity on the basis of the data output from the data buffer. The data buffer outputs n bits in the N bits to a generating unit, while shifting the data bit by bit at intervals of k cycles of a clock. The n bits in the N bits are combination of bits based on a determinant complying with the hamming code. The decoding unit identifies a bit position of an error in the data held in the data buffer using the syndrome held in the syndrome holding unit and causes the data buffer to correct the error.

Abstract: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or non-selected, based on an input signal. They also include an address signal input section configured to provide a signal to address the memory chip, based on an input signal. They further include a select address signal input section configured to make the plurality of memory chips selected or non-selected, based on an input signal, and configured divertible to the address signal input section.

Abstract: A semiconductor integrated circuit includes a plurality of functional circuits, a plurality of signal transmission lines disposed to interconnect among the functional circuits for transfer of a plurality of control signals which are to be supplied to respective functional circuits and are different in timing from one another, and a control circuit for generation of the control signals. The control circuit has a plurality of stages of control signal generator circuits that generate and issue the control signals respectively. The control signal generator circuits are specifically linked together so that when one generator circuit at a certain stage generates at its output a control signal to be transferred over a corresponding signal line, another circuit at the next stage is activated in response to receipt of this control signal.