Abstract: A semiconductor processing device (10) of the present invention includes a processing circuit (1), a digital-analog conversion circuit (2), an output control circuit (3), at least one output port circuit (4), a connection control circuit (5), and an output switch circuit (6). The output port circuit (4) includes an output buffer (41), a first switch element (SW1), and a second switch element (SW2, SW3). When the second switch element is connected to the side of an output amplifier (42), the output port circuit (4) controls the ON resistance of a P channel MOS transistor (41a) and an N channel MOS transistor (41b) based on a signal amplified at the output amplifier (42) to output an analog signal from the output buffer (41).

Abstract: A pulse transmission technique is used for wireless communication between a microcomputer (13) having a debugging support circuit (17) and a debugger (13). The pulse transmission technique is based on magnetic field coupling between a first coil (14) provided for the microcomputer and a second coil (8) coupled with the debugger. During an initialization operation, the microcomputer performs a process of configuring a communication condition of the wireless communication to perform the wireless communication. The microcomputer awaits control from the debugger when the microcomputer establishes communication with the debugger. The debugger awaits establishment of the communication and proceeds to control of the microcomputer in accordance with the wireless communication. It is possible to provide contactless interface for system debugging without the need for a large antenna or a large-scale circuit for modulation and demodulation.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A pulse transmission technique is used for wireless communication between a microcomputer (13) having a debugging support circuit (17) and a debugger (13). The pulse transmission technique is based on magnetic field coupling between a first coil (14) provided for the microcomputer and a second coil (8) coupled with the debugger. During an initialization operation, the microcomputer performs a process of configuring a communication condition of the wireless communication to perform the wireless communication. The microcomputer awaits control from the debugger when the microcomputer establishes communication with the debugger. The debugger awaits establishment of the communication and proceeds to control of the microcomputer in accordance with the wireless communication. It is possible to provide contactless interface for system debugging without the need for a large antenna or a large-scale circuit for modulation and demodulation.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

Abstract: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range.

Abstract: A phase-locked loop (PLL) circuit includes a low-pass filter, a voltage controlled oscillator that produces a PLL signal having a frequency that differs according to a control voltage supplied by the low-pass filter, a phase detector which receives the PLL signal and a reference signal and detects a phase difference between them to produce an error signal, and a charge pump that, in response to the error signal, supplies a charge to the low-pass filter or extracts a charge from the low-pass filter. The charge pump includes a variable resistance element the resistance of which varies when the error signal is applied, thereby nonlinearly adjusting the charge supplied to or extracted from the low-pass filter with respect to the duration of the error signal from the phase detector.