Abstract: An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.

Abstract: An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.