Abstract: A pressurized structure panel for forming a pressurized space pressurized inside includes a panel structure having a panel body to receive the pressure, a rib provided in the panel body, and a hollow part formed by the panel body and the rib, a radiation shielding material provided in the hollow part, and a debris bumper provided outside the panel structure and provided spaced apart from the panel structure by a certain spacing. The radiation shielding material includes a material containing hydrogen atoms in molecules.

Abstract: A submersible pump (100) is a submersible pump (100) in which a one-sided waterway (6) extending along a rotation shaft (1) is provided on one side of a submersible pump main body (100a), and includes an impeller (4); and a pump casing (5) in which the impeller (4) is arranged, in which the pump casing (5) includes a tongue portion (53) that is arranged between a pump chamber (5a) in which the impeller (4) is arranged and an inlet opening (6a) of the one-sided waterway (6) when viewed from an axial direction of the rotation shaft (1), and a connection waterway (54) that is provided between the tongue portion (53) and an inner surface (55) of the pump casing (5), and is directly connected to the inlet opening (6a) from an upstream side when viewed from the axial direction of the rotation shaft (1).

Abstract: A submersible pump (100) is a submersible pump (100) in which a one-sided waterway (6) extending along a rotation shaft (1) is provided on one side of a submersible pump main body (100a), and includes an impeller (4); and a pump casing (5) in which the impeller (4) is arranged, in which the pump casing (5) includes a tongue portion (53) that is arranged between a pump chamber (5a) in which the impeller (4) is arranged and an inlet opening (6a) of the one-sided waterway (6) when viewed from an axial direction of the rotation shaft (1), and a connection waterway (54) that is provided between the tongue portion (53) and an inner surface (55) of the pump casing (5), and is directly connected to the inlet opening (6a) from an upstream side when viewed from the axial direction of the rotation shaft (1).

Abstract: A pressurized structure panel for forming a pressurized space pressurized inside includes a panel structure having a panel body to receive the pressure, a rib provided in the panel body, and a hollow part formed by the panel body and the rib, a radiation shielding material provided in the hollow part, and a debris bumper provided outside the panel structure and provided spaced apart from the panel structure by a certain spacing. The radiation shielding material includes a material containing hydrogen atoms in molecules.

Abstract: The purpose of the present invention is to provide a bonded structure, a method for manufacturing the same, and a bonding state detection method which are capable of determining whether or not members are bonded together appropriately. A bonded structure 10 includes a laminated sheet 12A, a laminated sheet 12B, an adhesive 14 that bonds the laminated sheet 12A and the laminated sheet 12B together, and a distributed optical fiber 16 sandwiched between the laminated sheet 12A and the laminated sheet 12B. The cross-sectional shape of the distributed optical fiber 16 is deformed in accordance with the bonding state.

Abstract: The purpose of the present invention is to provide a bonded structure, a method for manufacturing the same, and a bonding state detection method which are capable of determining whether or not members are bonded together appropriately. A bonded structure 10 includes a laminated sheet 12A, a laminated sheet 12B, an adhesive 14 that bonds the laminated sheet 12A and the laminated sheet 12B together, and a distributed optical fiber 16 sandwiched between the laminated sheet 12A and the laminated sheet 12B. The cross-sectional shape of the distributed optical fiber 16 is deformed in accordance with the bonding state.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Abstract: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.

Abstract: A gate electrode of a MOS transistor connected with a word line and a bit line in an SRAM has a projection extending in a direction away from a contact electrically connecting a drain region of the MOS transistor and the bit line. A contact electrically connecting the gate electrode and the word line is provided in the projection of the gate electrode.

Abstract: In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input into a write control circuit, to delay start of the write operation until termination of the read operation. This can delay the timing of activating a write word line by a write row decoder behind the timing of activating a read word line by a read row decoder, to allow the read operation first followed by the write operation. Therefore, since the read operation is performed while the write word line being kept closed, the trouble of data processing becoming uncertain due to addition of the load of a write bit line to a read bit line can be prevented.