Patents by Inventor Yutaro Ebata

Yutaro Ebata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10199338
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20160284652
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 29, 2016
    Inventors: Taku KANAOKA, Masashi SAHARA, Yoshio FUKAYAMA, Yutaro EBATA, Kazuhisa HIGUCHI, Koji FUJISHIMA
  • Patent number: 8778790
    Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tota Maitani, Yutaro Ebata
  • Publication number: 20140159245
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicants: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku KANAOKA, Masashi SAHARA, Yoshio FUKAYAMA, Yutaro EBATA, Kazuhisa HIGUCHI, Koji FUJISHIMA
  • Patent number: 8669659
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: March 11, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20120205788
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Inventors: TAKU KANAOKA, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20120193787
    Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tota MAITANI, Yutaro EBATA
  • Patent number: 8183691
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: May 22, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI System Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20100252924
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: June 17, 2010
    Publication date: October 7, 2010
    Inventors: TAKU KANAOKA, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 7759804
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: July 20, 2010
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20080122085
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: January 25, 2008
    Publication date: May 29, 2008
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 7342302
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: March 11, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Publication number: 20060289998
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: July 20, 2006
    Publication date: December 28, 2006
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 7102223
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: September 5, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima