Abstract: A Doherty amplifier includes: a carrier amplifier that amplifies a first signal; a peak amplifier that amplifies a second signal; and a synthesis circuit that synthesizes the first signal amplified by the carrier amplifier and the second signal amplified by the peak amplifier, and the synthesis circuit includes a bandpass filter circuit that includes parasitic capacitances at respective output sides of the carrier amplifier and the peak amplifier as capacitors.

Abstract: A transistor characteristics simulation device uses a transistor equivalent circuit model, in which the transistor equivalent circuit model includes a trap equivalent circuit for modifying a level of a trap of a transistor by an electric field intensity, the trap equivalent circuit corresponding to a physical model of Poole-Frenkel effect.

Abstract: A signal to be amplified is applied to a gate terminal of an amplifier element that amplifies the signal and that is a transistor, the bias circuit includes: a switching element having a first terminal and a second terminal, the first terminal being electrically connected to the gate terminal; and a trap compensation element having a third terminal and a fourth terminal, the third terminal being connected to the second terminal. Further, the bias circuit includes a control circuit to apply a bias voltage to the gate terminal. Further, the bias circuit includes a voltage application circuit to apply a first voltage to the fourth terminal when the signal to be amplified is a transmission signal, and apply a second voltage to the fourth terminal when the signal to be amplified is a reception signal, the second voltage being a negative voltage.

Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

Abstract: Gate fingers extending symmetrically from both sides of gate connecting portions, drain electrodes adjacent to both the gate fingers extending from both the sides of the gate connecting portions, and source electrodes respectively adjacent to the gate fingers extending from both the sides of the gate connecting portions are included. Gate air bridges connect the gate connecting portions and a gate routing line while straddling the source electrodes.

Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.

Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

Abstract: A semiconductor device includes: an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.

Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).

Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.

Abstract: A semiconductor device includes; an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.

Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.

Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.

Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).

Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.

Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.

Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.