Patents by Inventor Yutaro YAMAGUCHI

Yutaro YAMAGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11025205
    Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 1, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Eigo Kuwata, Yutaro Yamaguchi
  • Publication number: 20210005535
    Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Shintaro SHINJO, Koji YAMANAKA
  • Patent number: 10797141
    Abstract: A semiconductor device includes: an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 6, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10777550
    Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 15, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10741700
    Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Publication number: 20200235215
    Abstract: A semiconductor device includes; an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.
    Type: Application
    Filed: July 25, 2016
    Publication date: July 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20200152803
    Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.
    Type: Application
    Filed: May 18, 2017
    Publication date: May 14, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20190372532
    Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.
    Type: Application
    Filed: February 22, 2017
    Publication date: December 5, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Eigo KUWATA, Yutaro YAMAGUCHI
  • Publication number: 20190296010
    Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).
    Type: Application
    Filed: December 16, 2016
    Publication date: September 26, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Patent number: 9570599
    Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 14, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaro Yamaguchi, Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka
  • Patent number: 9407216
    Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: August 2, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsuo Kohama, Yutaro Yamaguchi, Naoko Nitta, Kenji Mukai, Hiroshi Otsuka, Kenichi Horiguchi, Morishige Hieda, Koji Yamanaka, Satoshi Miho
  • Publication number: 20150249150
    Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.
    Type: Application
    Filed: December 17, 2012
    Publication date: September 3, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Toshiyuki OISHI, Hiroshi OTSUKA, Koji YAMANAKA
  • Patent number: 9111061
    Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: August 18, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Otsuka, Toshiyuki Oishi, Yutaro Yamaguchi, Naoki Kosaka, Shinichi Miwa, Koji Yamanaka
  • Publication number: 20150207476
    Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.
    Type: Application
    Filed: September 21, 2012
    Publication date: July 23, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuo Kohama, Yutaro Yamaguchi, Naoko Nitta, Kenji Mukai, Hiroshi Otsuka, Kenichi Horiguchi, Morishige Hieda, Koji Yamanaka, Satoshi Miho
  • Publication number: 20140019096
    Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.
    Type: Application
    Filed: December 26, 2012
    Publication date: January 16, 2014
    Inventors: Hiroshi OTSUKA, Toshiyuki OISHI, Yutaro YAMAGUCHI, Naoki KOSAKA, Shinichi MIWA, Koji YAMANAKA