Patents by Inventor Yu Ting Yeh
Yu Ting Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154447Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.Type: ApplicationFiled: August 29, 2023Publication date: May 9, 2024Applicant: PEGATRON CORPORATIONInventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
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Publication number: 20240136183Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Patent number: 11918882Abstract: An interactive exercise apparatus for guiding a user to perform an exercise includes a display device and a detecting device. The display device is configured to display video imagery which shows an instructor image and at least one motion check image. The motion check image corresponds to a predetermined one of a plurality of body parts of the user, which has a motion guide track and a motion achievement evaluation. The detecting device is configured to detect displacement of the body parts. The motion guide track is displayed on a predetermined position of the video imagery with a predetermined track pattern, corresponding to a movement path of the predetermined body part when the user follows movements demonstrated by the instructor image to perform the exercise. The motion achievement evaluation indicates a matching degree determined according to the displacement of the predetermined body part detected by the detecting device.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: Johnson Health Tech Co., Ltd.Inventors: Hsin-Huang Chiang, Yu-Chieh Lee, Ning Chuang, Wei-Ting Weng, Cheng-Ho Yeh
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Publication number: 20230253494Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.Type: ApplicationFiled: June 22, 2022Publication date: August 10, 2023Inventors: Kuo-Hsuan Lo, Chien-Hao Huang, Yu-Ting Yeh, Chu-Feng Chen, Wu-Te Weng
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Publication number: 20230045843Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.Type: ApplicationFiled: May 19, 2022Publication date: February 16, 2023Inventors: Yu-Ting Yeh, Kuo-Hsuan Lo, Chien-Hao Huang, Chu-Feng Chen, Wu-Te Weng
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Patent number: 10622473Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.Type: GrantFiled: August 19, 2018Date of Patent: April 14, 2020Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Chu-Feng Chen, YU-Ting Yeh
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Publication number: 20190115468Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.Type: ApplicationFiled: August 19, 2018Publication date: April 18, 2019Inventors: Tsung-Yi Huang, Chu-Feng Chen, Yu-Ting Yeh
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Patent number: 9378883Abstract: A transformer structure includes a first conductive plate, a second conductive plate, a circuit board and a core assembly. The first conductive plate has a first through hole and two first pins, and the first pins are formed by bending two ends of the first conductive plate respectively. The second conductive plate is installed opposite to the first conductive plate and has a second through hole and two second pins, and second pins are formed by bending the two ends of the second conductive plate respectively. The circuit board includes a winding, a positioning portion and a third through hole. The core assembly is electromagnetically coupled to the first conductive plate, the circuit board and the second conductive plate and passed through the first, second and third through holes to provide a high amperage and low-profile transformer structure.Type: GrantFiled: September 24, 2014Date of Patent: June 28, 2016Assignee: CHICONY POWER TECHNOLOGIES CO., LTD.Inventors: Hsien-Yi Tsai, Po-Ting Lin, Yu-Ting Yeh, Chi-Hsien Weng
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Publication number: 20160086718Abstract: A transformer structure includes a first conductive plate, a second conductive plate, a circuit board and a core assembly. The first conductive plate has a first through hole and two first pins, and the first pins are formed by bending two ends of the first conductive plate respectively. The second conductive plate is installed opposite to the first conductive plate and has a second through hole and two second pins, and second pins are formed by bending the two ends of the second conductive plate respectively. The circuit board includes a winding, a positioning portion and a third through hole. The core assembly is electromagentically coupled to the first conductive plate, the circuit board and the second conductive plate and passed through the first, second and third through holes to provide a high amperage and low-profile transformer structure.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Hsien-Yi TSAI, Po-Ting LIN, Yu-Ting YEH, Chi-Hsien WENG
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Patent number: 8742498Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.Type: GrantFiled: November 3, 2011Date of Patent: June 3, 2014Assignee: United Microelectronics Corp.Inventors: Fu-Chun Chien, Ching-Wei Teng, Nien-Chung Li, Chih-Chung Wang, Te-Yuan Wu, Li-Che Chen, Chih-Chun Pu, Yu-Ting Yeh, Kuan-Wen Lu
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Publication number: 20130113048Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Fu-Chun CHIEN, Ching-Wei Teng, Nien-Chung Li, Chih-Chung Wang, Te-Yuan Wu, Li-Che Chen, Chih-Chun Pu, Yu-Ting Yeh, Kuan-Wen Lu
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Publication number: 20100041965Abstract: In accordance with one aspect of the present invention, an electrical sleep assistant device, which comprises a handheld case, a display panel, a plurality of biosensors, and a calculation module, is provided. The case has a surface. The display panel is disposed on the surface of the case. The plurality of biosensors are disposed on the surface of the case for collecting a plurality of physiological information. The calculation module is disposed in the case, and coupled to the display panel and the plurality of biosensors. Preferably, a plurality of buttons disposed on the surface of the case, and coupled to the calculation module.Type: ApplicationFiled: August 7, 2009Publication date: February 18, 2010Applicant: National Taiwan UniversityInventors: Shih-Chung Kang, Rayleigh Ping-Ying Chiang, Peter Liu, Zai-Ting Yeh, Chia-Hsuan Chiang, Hung Lin Chi, Yu Ting Yeh, I-Ling Chen