Abstract: A semiconductor device disclosed herein includes an interconnection structure over a substrate, a first magnetic layer over the interconnection structure, one or more conductive features over the first magnetic layer, a dielectric layer over the first magnetic layer and the one or more conductive features, and a second magnetic layer over the dielectric layer. In some embodiments, the one or more conductive features include a textured top surface.

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

Abstract: A transformer structure includes a first conductive plate, a second conductive plate, a circuit board and a core assembly. The first conductive plate has a first through hole and two first pins, and the first pins are formed by bending two ends of the first conductive plate respectively. The second conductive plate is installed opposite to the first conductive plate and has a second through hole and two second pins, and second pins are formed by bending the two ends of the second conductive plate respectively. The circuit board includes a winding, a positioning portion and a third through hole. The core assembly is electromagnetically coupled to the first conductive plate, the circuit board and the second conductive plate and passed through the first, second and third through holes to provide a high amperage and low-profile transformer structure.

Abstract: A transformer structure includes a first conductive plate, a second conductive plate, a circuit board and a core assembly. The first conductive plate has a first through hole and two first pins, and the first pins are formed by bending two ends of the first conductive plate respectively. The second conductive plate is installed opposite to the first conductive plate and has a second through hole and two second pins, and second pins are formed by bending the two ends of the second conductive plate respectively. The circuit board includes a winding, a positioning portion and a third through hole. The core assembly is electromagentically coupled to the first conductive plate, the circuit board and the second conductive plate and passed through the first, second and third through holes to provide a high amperage and low-profile transformer structure.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: In accordance with one aspect of the present invention, an electrical sleep assistant device, which comprises a handheld case, a display panel, a plurality of biosensors, and a calculation module, is provided. The case has a surface. The display panel is disposed on the surface of the case. The plurality of biosensors are disposed on the surface of the case for collecting a plurality of physiological information. The calculation module is disposed in the case, and coupled to the display panel and the plurality of biosensors. Preferably, a plurality of buttons disposed on the surface of the case, and coupled to the calculation module.