Patents by Inventor YUTO YAMATO

YUTO YAMATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240336996
    Abstract: A plated steel sheet comprises a plated layer on a surface of a steel sheet, in which in the plated layer, the total amount ?A of Sn, Bi, and In is less than 0.75%, the total amount ?B of Ca, Y, La, and Ce is 0.03 to 0.60%, the total amount ?C of Cr, Ti, Ni, Co, V, Nb, Cu, and Mn is 0 to 1.00%, Sn?Si, and 20.0?Mg/Si are satisfied, and in an X-ray diffraction pattern of a surface of the plated layer, an X-ray diffraction peak of Al2.15Zn1.85Ca, an X-ray diffraction peak of CaZn2, and an X-ray diffraction peak of ??-MgZn2 satisfy a predetermined relationship.
    Type: Application
    Filed: August 16, 2022
    Publication date: October 10, 2024
    Applicant: NIPPON STEEL CORPORATION
    Inventors: Kohei TOKUDA, Mamoru SAITO, Yuto FUKUDA, Yasuto GOTO, Yasuhiro MAJIMA, Naoyuki YAMATO, Fumiaki NAKAMURA, Hidetoshi SHINDO, Koji KAWANISHI, Kenichiro MATSUMURA, Hiroshi TAKEBAYASHI
  • Patent number: 11699553
    Abstract: A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: July 11, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuto Yamato, Takashi Asai, Takayuki Hattori
  • Patent number: 11551873
    Abstract: A method of producing a multi-layer ceramic electronic component includes: producing a multi-layer unit including ceramic layers that are laminated in a first direction, internal electrodes that are disposed between the ceramic layers, and a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed on the side surface; sintering the multi-layer unit; and forming a side margin on the side surface of the sintered multi-layer unit.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 10, 2023
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Takayuki Hattori, Yuto Yamato
  • Patent number: 11424076
    Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yuto Yamato, Takayuki Hattori, Takashi Asai, Hisamitsu Shizuno, Keisuke Ishii
  • Publication number: 20210366658
    Abstract: A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Yuto YAMATO, Takashi ASAI, Takayuki HATTORI
  • Publication number: 20210183583
    Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Inventors: Yuto YAMATO, Takayuki HATTORI, Takashi ASAI, Hisamitsu SHIZUNO, Keisuke ISHII
  • Patent number: 10964482
    Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yuto Yamato, Takayuki Hattori, Takashi Asai, Hisamitsu Shizuno, Keisuke Ishii
  • Publication number: 20190355521
    Abstract: A method of producing a multi-layer ceramic electronic component includes: producing a multi-layer unit including ceramic layers that are laminated in a first direction, internal electrodes that are disposed between the ceramic layers, and a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed on the side surface; sintering the multi-layer unit; and forming a side margin on the side surface of the sintered multi-layer unit.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 21, 2019
    Inventors: TAKAYUKI HATTORI, YUTO YAMATO
  • Publication number: 20190189352
    Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventors: YUTO YAMATO, TAKAYUKI HATTORI, TAKASHI ASAI, HISAMITSU SHIZUNO, KEISUKE ISHII