Patents by Inventor YUTO YAMATO
YUTO YAMATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240336996Abstract: A plated steel sheet comprises a plated layer on a surface of a steel sheet, in which in the plated layer, the total amount ?A of Sn, Bi, and In is less than 0.75%, the total amount ?B of Ca, Y, La, and Ce is 0.03 to 0.60%, the total amount ?C of Cr, Ti, Ni, Co, V, Nb, Cu, and Mn is 0 to 1.00%, Sn?Si, and 20.0?Mg/Si are satisfied, and in an X-ray diffraction pattern of a surface of the plated layer, an X-ray diffraction peak of Al2.15Zn1.85Ca, an X-ray diffraction peak of CaZn2, and an X-ray diffraction peak of ??-MgZn2 satisfy a predetermined relationship.Type: ApplicationFiled: August 16, 2022Publication date: October 10, 2024Applicant: NIPPON STEEL CORPORATIONInventors: Kohei TOKUDA, Mamoru SAITO, Yuto FUKUDA, Yasuto GOTO, Yasuhiro MAJIMA, Naoyuki YAMATO, Fumiaki NAKAMURA, Hidetoshi SHINDO, Koji KAWANISHI, Kenichiro MATSUMURA, Hiroshi TAKEBAYASHI
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Patent number: 11699553Abstract: A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.Type: GrantFiled: May 19, 2021Date of Patent: July 11, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Yuto Yamato, Takashi Asai, Takayuki Hattori
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Patent number: 11551873Abstract: A method of producing a multi-layer ceramic electronic component includes: producing a multi-layer unit including ceramic layers that are laminated in a first direction, internal electrodes that are disposed between the ceramic layers, and a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed on the side surface; sintering the multi-layer unit; and forming a side margin on the side surface of the sintered multi-layer unit.Type: GrantFiled: May 16, 2019Date of Patent: January 10, 2023Assignee: Taiyo Yuden Co., Ltd.Inventors: Takayuki Hattori, Yuto Yamato
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Patent number: 11424076Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.Type: GrantFiled: February 23, 2021Date of Patent: August 23, 2022Assignee: Taiyo Yuden Co., Ltd.Inventors: Yuto Yamato, Takayuki Hattori, Takashi Asai, Hisamitsu Shizuno, Keisuke Ishii
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Publication number: 20210366658Abstract: A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.Type: ApplicationFiled: May 19, 2021Publication date: November 25, 2021Applicant: TAIYO YUDEN CO., LTD.Inventors: Yuto YAMATO, Takashi ASAI, Takayuki HATTORI
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Publication number: 20210183583Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.Type: ApplicationFiled: February 23, 2021Publication date: June 17, 2021Inventors: Yuto YAMATO, Takayuki HATTORI, Takashi ASAI, Hisamitsu SHIZUNO, Keisuke ISHII
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Patent number: 10964482Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.Type: GrantFiled: December 14, 2018Date of Patent: March 30, 2021Assignee: Taiyo Yuden Co., Ltd.Inventors: Yuto Yamato, Takayuki Hattori, Takashi Asai, Hisamitsu Shizuno, Keisuke Ishii
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Publication number: 20190355521Abstract: A method of producing a multi-layer ceramic electronic component includes: producing a multi-layer unit including ceramic layers that are laminated in a first direction, internal electrodes that are disposed between the ceramic layers, and a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed on the side surface; sintering the multi-layer unit; and forming a side margin on the side surface of the sintered multi-layer unit.Type: ApplicationFiled: May 16, 2019Publication date: November 21, 2019Inventors: TAKAYUKI HATTORI, YUTO YAMATO
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Publication number: 20190189352Abstract: A multi-layer ceramic capacitor having a weight of 8 mg or more includes a capacitance forming unit and a protective unit. The capacitance forming unit includes internal electrodes that are laminated in a first direction and includes end portions, positions of the end portions in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The protective unit covers the capacitance forming unit in the first direction and the second direction and includes an outer surface, a shortest distance between the outer surface and the end portion of an outermost layer in the internal electrodes in the first direction exceeding 10 ?m.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Inventors: YUTO YAMATO, TAKAYUKI HATTORI, TAKASHI ASAI, HISAMITSU SHIZUNO, KEISUKE ISHII