Abstract: Provided is an electric cable driving mechanism having a self-return function. The electric cable driving mechanism includes a housing assembly, an electric motor, a three-stage transmission mechanism and a multifunctional nut, the three-stage transmission mechanism includes a coil spring assembly, the electric motor is fixed to the housing assembly, and the three-stage transmission mechanism and the multifunctional nut are mounted in the housing assembly; and the multifunctional nut includes two cable mounting grooves and is in transmission connection to the electric motor by means of the three-stage transmission mechanism. According to the electric cable driving mechanism having a self-return function of the present disclosure, the three-stage transmission mechanism is used, and outputs a larger force compared with two-stage transmission; and a split multifunctional screw rod is easy to mount, such that mounting of a coil spring during assembly is prevented from scratching the screw rod.

Abstract: A semiconductor structure and a preparation method therefor are provided. The semiconductor structure includes: a substrate, a gate dielectric layer, a first gate in a PMOS region, and a second gate in an NMOS region. The substrate includes a PMOS region and an NMOS region; the gate dielectric layer is located on the substrate of the PMOS region and of the NMOS region. The first gate includes a first work function layer and a first gate electrode layer that are stacked. The first work function layer is formed based on a first doping treatment of an initial work function layer. The second gate includes a second work function layer and a second gate electrode layer that are stacked. The semiconductor structure and the preparing method provided in the present disclosure can alleviate uneven etching of a PMOS transistor and an NMOS transistor and improve the yield and reliability of semiconductor devices.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, having a first region and a second region; a first gate structure positioned in the first region and a second gate structure positioned in the second region, the first gate structure being a high dielectric constant gate including a first gate electrode layer and a high dielectric constant layer, and the second gate structure including a second gate electrode layer and an oxide insulating layer; a spacer and an interlayer dielectric layer, positioned on the first gate structure and the second gate structure, the spacer and the interlayer dielectric layer covering a part of the second gate structure, the substrate, and the first gate structure; and a second contact plug, penetrating through the spacer and the interlayer dielectric layer and being in contact with the substrate.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, including a doped region; a recess, located in the doped region; and a gradient layer, filling the recess, wherein a doping concentration of the gradient layer varies gradually from a bottom of the recess upwards.

Abstract: A semiconductor structure includes a substrate and a gate stack structure located on the substrate. The gate stack structure includes: a high-K dielectric layer, a first barrier layer in contact with the high-K dielectric layer, a work function layer located on a side of the high-K dielectric layer away from the substrate, and a gate electrode layer located on a side of the work function layer away from the substrate. The first barrier layer contains the same metal element as the high-K dielectric layer.

Abstract: The present invention provides a radar target detection method based on estimation before detection (EBD), which comprises: obtaining pre-detect targets (PDTs) based on conventional pulse-Doppler processing and pre-detection; estimating ranges and speeds of PDTs, i.e., performing parameter EBD; establishing a dimension-reduction observation model of a received signal based on PDTs and parameter thereof; reconstructing a target vector in the dimension-reduction observation model based on a sparse recovery algorithm; and designing a generalized likelihood ratio detector based on the reconstruction result for target detection. The method of the present invention can significantly reduce the radar signal processing loss, and the target detector used in the method has the constant false alarm rate (CFAR) property, so that the weak target detection performance can be greatly improved.

Abstract: Embodiments relate to a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a semiconductor substrate; a dielectric layer positioned on the semiconductor substrate; and a gate structure, including a bandgap-tunable material layer. The bandgap-tunable material layer is positioned on the dielectric layer, a Fermi level of the bandgap-tunable material layer shifts to a conduction band when electrons inflow, and the Fermi level of the bandgap-tunable material layer shifts to a valence band when the electrons outflow. The semiconductor structure and the fabrication method thereof can effectively reduce fabrication difficulty of the gate structure.

Abstract: Embodiments relate to the field of semiconductor technology, and propose a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a channel layer including a group III-V semiconductor and a group III-V semiconductor layer, the group III-V semiconductor and the group III-V semiconductor layer forming a heterojunction; a gate structure positioned on the channel layer, the gate structure including a gallium oxide layer, a gate oxide layer, and a gate electrode stacked in sequence; a source electrode positioned at an end of the heterojunction; and a drain electrode positioned at other end of the heterojunction.

Abstract: Embodiments provide a transistor structure, a semiconductor structure and a fabrication method thereof. The method for fabricating a transistor structure includes: providing a substrate; forming a channel layer on an upper surface of the substrate, the channel layer including a two-dimensional layered transition metal material layer; forming a source and a drain on two opposite sides of the channel layer, respectively; forming a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source, and the drain; and forming a gate on an upper surface of the gate dielectric layer, the gate being positioned at least directly above the channel layer.