Patents by Inventor Yuu Ueda

Yuu Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8554455
    Abstract: An IIS system that performs control related to intermittent stopping of engine operation by idling stop control is applied to an internal combustion engine including a VVT mechanism that makes the valve timing of an engine valve variable and has an intermediate lock mechanism that mechanically locks the valve timing at an intermediate lock position between a most retarded position and a most advanced position. The IIS system is configured to inhibit the engine operation from being intermittently stopped at the occurrence of a failure of the VVT mechanism to avoid the internal combustion engine from being prevented from being restarted after the intermittent stop depending on the occurrence of the failure of the VVT mechanism.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 8, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yoshiaki Miyazato, Toshio Imamura, Yuu Yokoyama, Satoshi Yoshi, Yoshiki Endo, Yuu Ueda, Hiroyuki Ishii
  • Publication number: 20130152887
    Abstract: An IIS system that performs control related to intermittent stopping of engine operation by idling stop control is applied to an internal combustion engine including a VVT mechanism that makes the valve timing of an engine valve variable and has an intermediate lock mechanism that mechanically locks the valve timing at an intermediate lock position between a most retarded position and a most advanced position. The IIS system is configured to inhibit the engine operation from being intermittently stopped at the occurrence of a failure of the VVT mechanism to avoid the internal combustion engine from being prevented from being restarted after the intermittent stop depending on the occurrence of the failure of the VVT mechanism.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 20, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshiaki Miyazato, Toshio Imamura, Yuu Yokoyama, Satoshi Yoshi, Yoshiki Endo, Yuu Ueda, Hiroyuki Ishii
  • Patent number: 6124181
    Abstract: In a method for manufacturing a bipolar transistor, a first insulating layer, a first polycrystalline silicon layer of a second conductivity type, and a second insulating layer are sequentially formed on a semiconductor substrate of a first conductivity type. Then, the second insulating layer and the first polycrystalline silicon layer are patterned to form an opening therein. Then, the first insulating layer is over etched by using the second insulating layer and the first polycrystalline silicon layer as a mask. Then, a second polycrystalline silicon layer is formed on the entire surface. Then, an oxidizing process is performed upon the second polycrystalline silicon layer except for a part of the second polycrystalline silicon layer under the first polycrystalline silicon layer, and the oxidized part of the second polycrystalline silicon layer is removed by a wet etching process. Then, impurities of the second conductivity type are implanted into the semiconductor substrate to form a base region.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: September 26, 2000
    Assignee: NEC Corporation
    Inventor: Yuu Ueda
  • Patent number: 6027993
    Abstract: The present invention provides a method of forming an opening an insulation layer over a substrate. A photo-resist film with at least an opening is formed over a substrate. A first spacer layer is selectively formed within the opening of the photo-resist film. The photo-resist film is removed to have the first spacer layer remain over the substrate. An insulation layer is formed which extends over the first spacer layer and the substrate so that the insulation layer over the first spacer layer is higher in level than the insulation layer over the substrate. A second spacer layer is formed which extends over the insulation layer over the substrate so that the insulation layer over the first spacer layer is shown. Both the insulation layer over the first spacer layer and the second spacer layer are selectively removed so that the insulation layer over the substrate and the first spacer layer are shown.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Yuu Ueda