Patents by Inventor Yuu YAMAYOSE

Yuu YAMAYOSE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126950
    Abstract: A thermal analysis method and apparatus, and a computer program that enable highly accurate heat transfer simulation of a structure or space, while reducing calculation costs. By performing thermal analysis on a structure or space using the calculation meshes generated by initial dividing means, the spatial distribution of heat flux vectors J and temperature gradient vectors ?T are calculated; by calculating the volume integrals of the inner products J·?T of the heat flux vectors J and the temperature gradient vectors ?T for individual partitioned regions and acquiring the absolute values of the volume integrals, thermal management sensitivity indices are calculated for the partitioned regions. Subsequently, partition of calculation meshes and subdivision of partitioned regions are performed on a predetermined number of partitioned regions that indicate greater indices among the calculated thermal management sensitivity indices, for example one partitioned region.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yuu YAMAYOSE, Teruhisa SHIBAHARA, Masataka FUKUNISHI
  • Patent number: 10234413
    Abstract: According to one embodiment, an electronic device comprises a circuit board, an electrical component, and a measurement unit. The circuit board has a first face. The electrical component includes a second face electrically connected to the first face via a bonding material, a first end in a first direction along the second face, and a second end. The second end is opposite to the first end in the first direction. The measurement unit is configured to measure a characteristic changing depending on a conductivity of the bonding material. A first distance between the first face and the first end is shorter than a second distance between the first face and the second end. The measurement unit includes a first measurement unit configured to measure the characteristic of a part of the bonding material. The part is adjacent to the first end.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuu Yamayose, Tetsuya Kugimiya
  • Patent number: 9941177
    Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kentaro Kasa, Kazuya Fukuhara, Kazutaka Ishigo, Manabu Takakuwa, Yoshinori Hagio, Kazuhiro Segawa, Yuki Murasaka, Tetsuya Kugimiya, Yuu Yamayose, Yosuke Okamoto
  • Publication number: 20170271214
    Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 21, 2017
    Inventors: Kentaro KASA, Kazuya FUKUHARA, Kazutaka ISHIGO, Manabu TAKAKUWA, Yoshinori HAGIO, Kazuhiro SEGAWA, Yuki MURASAKA, Tetsuya KUGIMIYA, Yuu YAMAYOSE, Yosuke OKAMOTO
  • Patent number: 9699891
    Abstract: A substrate includes a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named. The substrate also includes a first wire and a second wire formed in a region below a corner of the semiconductor package. The first and second wires are configured to detect a change in electrical resistance value when the first wire or the second wire is disconnected. One of the first and second wires is connected to the first electrode pad or the second electrode pad. A break strength of each of the first wire and the second wire is lower than a break strength of the join-structure.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuu Yamayose, Kenji Hirohata
  • Publication number: 20160282291
    Abstract: According to one embodiment, an electronic device comprises a circuit board, an electrical component, and a measurement unit. The circuit board has a first face. The electrical component includes a second face electrically connected to the first face via a bonding material, a first end in a first direction along the second face, and a second end. The second end is opposite to the first end in the first direction. The measurement unit is configured to measure a characteristic changing depending on a conductivity of the bonding material. A first distance between the first face and the first end is shorter than a second distance between the first face and the second end. The measurement unit includes a first measurement unit configured to measure the characteristic of a part of the bonding material. The part is adjacent to the first end.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 29, 2016
    Inventors: Yuu YAMAYOSE, Tetsuya KUGIMIYA
  • Publication number: 20150171054
    Abstract: According to an embodiment, a semiconductor component includes a circuit board; a semiconductor chip; and a bond part formed by sintering a paste containing metal particles between the circuit board and the semiconductor chip to bond the circuit board and the semiconductor chip. The bond part includes a first area immediately under the semiconductor chip and a second area adjacent to the first area. The second area has a porosity equal to or lower than that of the first area.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 18, 2015
    Inventors: Yuu YAMAYOSE, Tetsuya KUGIMIYA, Kenji HIROHATA
  • Publication number: 20140091829
    Abstract: According to one embodiment, a semiconductor device includes a circuit board, a plurality of semiconductor chips stacked above the circuit board, first and second bumps, third and fourth bumps, and first and second detection units. The first and second bumps are provided in either a gap between the circuit board and the semiconductor chip or a gap between the two semiconductor chips. The third and fourth bumps are provided in any of gaps other than the gap in which the first and second bumps are provided. The first detection unit is electrically connected to the first bump to detect damage of the first bump and to generate a first signal indicating the damage of the first bump. The second detection unit is electrically connected to the third bump to detect damage of the third bump and to generate a second signal indicating the damage of the third bump.
    Type: Application
    Filed: August 29, 2013
    Publication date: April 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuu YAMAYOSE, Kenji HIROHATA
  • Publication number: 20120176149
    Abstract: A substrate includes a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named. The substrate also includes a first wire and a second wire formed in a region bellow a corner of the semiconductor package. The first and second wires are configured to detect a change in electrical resistance value when the first wire or the second wire is disconnected. One of the first and second wires is connected to the first electrode pad or the second electrode pad. A break strength of each of the first wire and the second wire is lower than a break strength of the join-structure.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuu YAMAYOSE, Kenji HIROHATA