Patents by Inventor Yuuichi Harada

Yuuichi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7476935
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: January 13, 2009
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Patent number: 7436024
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20060027863
    Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 9, 2006
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Hiroshi Kanemaru, Yoshihiro Ikura, Ryuu Saitou
  • Publication number: 20050145975
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 7, 2005
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Patent number: 6870223
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: March 22, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Publication number: 20030127687
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Application
    Filed: November 21, 2002
    Publication date: July 10, 2003
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Patent number: 4728208
    Abstract: A ribbon lifting mechanism usable for a typewriter including a holder turnably supported in a frame, a motor driven ribbon lifting cam and at least a cam follower operatively connected to the holder. Printing ribbon and correction tape are accommodated in the holder and either of them is located at the printing position by means of the ribbon lifting cam which is formed with a plurality of cam sections. The cam follower is actuated in accordance with cam sections on the ribbon lifting cam. The mechanism further includes a stopper member which serves to locate the printing ribbon at the printing position while it is engaged to the holder. The stopper member also serves to locate the correction tape at the printing position while it is disengaged from the holder.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: March 1, 1988
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takayuki Iwase, Yuuichi Harada